1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <regmap.h> 12 #include <reset.h> 13 14 #include <drm/drm_dp_helper.h> 15 16 #define ANALOGIX_DP_TX_SW_RESET 0x14 17 #define ANALOGIX_DP_FUNC_EN_1 0x18 18 #define ANALOGIX_DP_FUNC_EN_2 0x1C 19 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 20 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 21 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 22 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C 23 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 24 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 25 26 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 27 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C 28 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 29 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 30 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58 31 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C 32 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60 33 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 34 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 35 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C 36 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 37 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 38 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 39 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C 40 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80 41 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 42 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 43 44 #define ANALOGIX_DP_PLL_REG_1 0xfc 45 #define ANALOGIX_DP_PLL_REG_2 0x9e4 46 #define ANALOGIX_DP_PLL_REG_3 0x9e8 47 #define ANALOGIX_DP_PLL_REG_4 0x9ec 48 #define ANALOGIX_DP_PLL_REG_5 0xa00 49 50 #define ANALOGIX_DP_BIAS 0x124 51 #define ANALOGIX_DP_PD 0x12c 52 53 #define ANALOGIX_DP_LANE_MAP 0x35C 54 55 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 56 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 57 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 58 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 59 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 60 61 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 62 63 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 64 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 65 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 66 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 67 #define ANALOGIX_DP_INT_STA 0x3DC 68 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 69 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 70 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 71 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 72 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 73 #define ANALOGIX_DP_INT_CTL 0x3FC 74 75 #define ANALOGIX_DP_SYS_CTL_1 0x600 76 #define ANALOGIX_DP_SYS_CTL_2 0x604 77 #define ANALOGIX_DP_SYS_CTL_3 0x608 78 #define ANALOGIX_DP_SYS_CTL_4 0x60C 79 80 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 81 #define ANALOGIX_DP_HDCP_CTL 0x648 82 83 #define ANALOGIX_DP_LINK_BW_SET 0x680 84 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 85 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 86 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 87 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 88 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 89 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 90 91 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 92 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 93 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 94 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 95 96 #define ANALOGIX_DP_M_VID_0 0x700 97 #define ANALOGIX_DP_M_VID_1 0x704 98 #define ANALOGIX_DP_M_VID_2 0x708 99 #define ANALOGIX_DP_N_VID_0 0x70C 100 #define ANALOGIX_DP_N_VID_1 0x710 101 #define ANALOGIX_DP_N_VID_2 0x714 102 103 #define ANALOGIX_DP_PLL_CTL 0x71C 104 #define ANALOGIX_DP_PHY_PD 0x720 105 #define ANALOGIX_DP_PHY_TEST 0x724 106 107 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 108 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 109 110 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 111 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 112 #define ANALOGIX_DP_AUX_CH_STA 0x780 113 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 114 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 115 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 116 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 117 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 118 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 119 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 120 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 121 122 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 123 124 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 125 126 /* ANALOGIX_DP_TX_SW_RESET */ 127 #define RESET_DP_TX (0x1 << 0) 128 129 /* ANALOGIX_DP_FUNC_EN_1 */ 130 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 131 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 132 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 133 #define AUD_FUNC_EN_N (0x1 << 3) 134 #define HDCP_FUNC_EN_N (0x1 << 2) 135 #define CRC_FUNC_EN_N (0x1 << 1) 136 #define SW_FUNC_EN_N (0x1 << 0) 137 138 /* ANALOGIX_DP_FUNC_EN_2 */ 139 #define SSC_FUNC_EN_N (0x1 << 7) 140 #define AUX_FUNC_EN_N (0x1 << 2) 141 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 142 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 143 144 /* ANALOGIX_DP_VIDEO_CTL_1 */ 145 #define VIDEO_EN (0x1 << 7) 146 #define HDCP_VIDEO_MUTE (0x1 << 6) 147 148 /* ANALOGIX_DP_VIDEO_CTL_4 */ 149 #define BIST_EN (0x1 << 3) 150 #define BIST_WIDTH(x) (((x) & 0x1) << 2) 151 #define BIST_TYPE(x) (((x) & 0x3) << 0) 152 153 /* ANALOGIX_DP_VIDEO_CTL_1 */ 154 #define IN_D_RANGE_MASK (0x1 << 7) 155 #define IN_D_RANGE_SHIFT (7) 156 #define IN_D_RANGE_CEA (0x1 << 7) 157 #define IN_D_RANGE_VESA (0x0 << 7) 158 #define IN_BPC_MASK (0x7 << 4) 159 #define IN_BPC_SHIFT (4) 160 #define IN_BPC_12_BITS (0x3 << 4) 161 #define IN_BPC_10_BITS (0x2 << 4) 162 #define IN_BPC_8_BITS (0x1 << 4) 163 #define IN_BPC_6_BITS (0x0 << 4) 164 #define IN_COLOR_F_MASK (0x3 << 0) 165 #define IN_COLOR_F_SHIFT (0) 166 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 167 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 168 #define IN_COLOR_F_RGB (0x0 << 0) 169 170 /* ANALOGIX_DP_VIDEO_CTL_3 */ 171 #define IN_YC_COEFFI_MASK (0x1 << 7) 172 #define IN_YC_COEFFI_SHIFT (7) 173 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 174 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 175 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 176 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 177 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 178 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 179 180 /* ANALOGIX_DP_VIDEO_CTL_8 */ 181 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 182 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 183 184 /* ANALOGIX_DP_VIDEO_CTL_10 */ 185 #define FORMAT_SEL (0x1 << 4) 186 #define INTERACE_SCAN_CFG (0x1 << 2) 187 #define VSYNC_POLARITY_CFG (0x1 << 1) 188 #define HSYNC_POLARITY_CFG (0x1 << 0) 189 190 /* ANALOGIX_DP_TOTAL_LINE_CFG_L */ 191 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) 192 193 /* ANALOGIX_DP_TOTAL_LINE_CFG_H */ 194 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) 195 196 /* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ 197 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) 198 199 /* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ 200 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) 201 202 /* ANALOGIX_DP_V_F_PORCH_CFG */ 203 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) 204 205 /* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ 206 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) 207 208 /* ANALOGIX_DP_V_B_PORCH_CFG */ 209 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) 210 211 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ 212 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 213 214 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ 215 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 216 217 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ 218 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 219 220 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ 221 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 222 223 /* ANALOGIX_DP_H_F_PORCH_CFG_L */ 224 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) 225 226 /* ANALOGIX_DP_H_F_PORCH_CFG_H */ 227 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) 228 229 /* ANALOGIX_DP_H_SYNC_CFG_L */ 230 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) 231 232 /* ANALOGIX_DP_H_SYNC_CFG_H */ 233 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) 234 235 /* ANALOGIX_DP_H_B_PORCH_CFG_L */ 236 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) 237 238 /* ANALOGIX_DP_H_B_PORCH_CFG_H */ 239 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) 240 241 /* ANALOGIX_DP_PLL_REG_1 */ 242 #define REF_CLK_24M (0x1 << 0) 243 #define REF_CLK_27M (0x0 << 0) 244 #define REF_CLK_MASK (0x1 << 0) 245 246 /* ANALOGIX_DP_LANE_MAP */ 247 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 248 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 249 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 250 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 251 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 252 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 253 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 254 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 255 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 256 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 257 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 258 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 259 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 260 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 261 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 262 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 263 264 /* ANALOGIX_DP_ANALOG_CTL_1 */ 265 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 266 267 /* ANALOGIX_DP_ANALOG_CTL_2 */ 268 #define SEL_24M (0x1 << 3) 269 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 270 271 /* ANALOGIX_DP_ANALOG_CTL_3 */ 272 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 273 #define VCO_BIT_600_MICRO (0x5 << 0) 274 275 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 276 #define PD_RING_OSC (0x1 << 6) 277 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 278 #define TX_CUR1_2X (0x1 << 2) 279 #define TX_CUR_16_MA (0x3 << 0) 280 281 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 282 #define CH3_AMP_400_MV (0x0 << 24) 283 #define CH2_AMP_400_MV (0x0 << 16) 284 #define CH1_AMP_400_MV (0x0 << 8) 285 #define CH0_AMP_400_MV (0x0 << 0) 286 287 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 288 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 289 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 290 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 291 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 292 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 293 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 294 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 295 296 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 297 #define VSYNC_DET (0x1 << 7) 298 #define PLL_LOCK_CHG (0x1 << 6) 299 #define SPDIF_ERR (0x1 << 5) 300 #define SPDIF_UNSTBL (0x1 << 4) 301 #define VID_FORMAT_CHG (0x1 << 3) 302 #define AUD_CLK_CHG (0x1 << 2) 303 #define VID_CLK_CHG (0x1 << 1) 304 #define SW_INT (0x1 << 0) 305 306 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 307 #define ENC_EN_CHG (0x1 << 6) 308 #define HW_BKSV_RDY (0x1 << 3) 309 #define HW_SHA_DONE (0x1 << 2) 310 #define HW_AUTH_STATE_CHG (0x1 << 1) 311 #define HW_AUTH_DONE (0x1 << 0) 312 313 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 314 #define AFIFO_UNDER (0x1 << 7) 315 #define AFIFO_OVER (0x1 << 6) 316 #define R0_CHK_FLAG (0x1 << 5) 317 318 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 319 #define PSR_ACTIVE (0x1 << 7) 320 #define PSR_INACTIVE (0x1 << 6) 321 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 322 #define HOTPLUG_CHG (0x1 << 2) 323 #define HPD_LOST (0x1 << 1) 324 #define PLUG (0x1 << 0) 325 326 /* ANALOGIX_DP_INT_STA */ 327 #define INT_HPD (0x1 << 6) 328 #define HW_TRAINING_FINISH (0x1 << 5) 329 #define RPLY_RECEIV (0x1 << 1) 330 #define AUX_ERR (0x1 << 0) 331 332 /* ANALOGIX_DP_INT_CTL */ 333 #define SOFT_INT_CTRL (0x1 << 2) 334 #define INT_POL1 (0x1 << 1) 335 #define INT_POL0 (0x1 << 0) 336 337 /* ANALOGIX_DP_SYS_CTL_1 */ 338 #define DET_STA (0x1 << 2) 339 #define FORCE_DET (0x1 << 1) 340 #define DET_CTRL (0x1 << 0) 341 342 /* ANALOGIX_DP_SYS_CTL_2 */ 343 #define CHA_CRI(x) (((x) & 0xf) << 4) 344 #define CHA_STA (0x1 << 2) 345 #define FORCE_CHA (0x1 << 1) 346 #define CHA_CTRL (0x1 << 0) 347 348 /* ANALOGIX_DP_SYS_CTL_3 */ 349 #define HPD_STATUS (0x1 << 6) 350 #define F_HPD (0x1 << 5) 351 #define HPD_CTRL (0x1 << 4) 352 #define HDCP_RDY (0x1 << 3) 353 #define STRM_VALID (0x1 << 2) 354 #define F_VALID (0x1 << 1) 355 #define VALID_CTRL (0x1 << 0) 356 357 /* ANALOGIX_DP_SYS_CTL_4 */ 358 #define FIX_M_AUD (0x1 << 4) 359 #define ENHANCED (0x1 << 3) 360 #define FIX_M_VID (0x1 << 2) 361 #define M_VID_UPDATE_CTRL (0x3 << 0) 362 363 /* ANALOGIX_DP_TRAINING_PTN_SET */ 364 #define SCRAMBLER_TYPE (0x1 << 9) 365 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 366 #define SCRAMBLING_DISABLE (0x1 << 5) 367 #define SCRAMBLING_ENABLE (0x0 << 5) 368 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 369 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 370 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 371 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 372 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 373 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 374 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 375 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 376 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 377 378 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 379 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 380 #define PRE_EMPHASIS_SET_SHIFT (3) 381 382 /* ANALOGIX_DP_DEBUG_CTL */ 383 #define PLL_LOCK (0x1 << 4) 384 #define F_PLL_LOCK (0x1 << 3) 385 #define PLL_LOCK_CTRL (0x1 << 2) 386 #define PN_INV (0x1 << 0) 387 388 /* ANALOGIX_DP_PLL_CTL */ 389 #define DP_PLL_PD (0x1 << 7) 390 #define DP_PLL_RESET (0x1 << 6) 391 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 392 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 393 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 394 395 /* ANALOGIX_DP_PHY_PD */ 396 #define DP_PHY_PD (0x1 << 5) 397 #define AUX_PD (0x1 << 4) 398 #define CH3_PD (0x1 << 3) 399 #define CH2_PD (0x1 << 2) 400 #define CH1_PD (0x1 << 1) 401 #define CH0_PD (0x1 << 0) 402 403 /* ANALOGIX_DP_PHY_TEST */ 404 #define MACRO_RST (0x1 << 5) 405 #define CH1_TEST (0x1 << 1) 406 #define CH0_TEST (0x1 << 0) 407 408 /* ANALOGIX_DP_AUX_CH_STA */ 409 #define AUX_BUSY (0x1 << 4) 410 #define AUX_STATUS_MASK (0xf << 0) 411 412 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 413 #define DEFER_CTRL_EN (0x1 << 7) 414 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 415 416 /* ANALOGIX_DP_AUX_RX_COMM */ 417 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 418 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 419 420 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 421 #define BUF_CLR (0x1 << 7) 422 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 423 424 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 425 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 426 #define AUX_TX_COMM_MASK (0xf << 0) 427 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 428 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 429 #define AUX_TX_COMM_MOT (0x1 << 2) 430 #define AUX_TX_COMM_WRITE (0x0 << 0) 431 #define AUX_TX_COMM_READ (0x1 << 0) 432 433 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 434 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 435 436 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 437 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 438 439 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 440 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 441 442 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 443 #define ADDR_ONLY (0x1 << 1) 444 #define AUX_EN (0x1 << 0) 445 446 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 447 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 448 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 449 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 450 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 451 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 452 #define VIDEO_MODE_MASK (0x1 << 0) 453 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 454 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 455 456 #define DP_TIMEOUT_LOOP_COUNT 100 457 #define MAX_CR_LOOP 5 458 #define MAX_EQ_LOOP 5 459 460 /* I2C EDID Chip ID, Slave Address */ 461 #define I2C_EDID_DEVICE_ADDR 0x50 462 #define I2C_E_EDID_DEVICE_ADDR 0x30 463 464 #define EDID_BLOCK_LENGTH 0x80 465 #define EDID_HEADER_PATTERN 0x00 466 #define EDID_EXTENSION_FLAG 0x7e 467 #define EDID_CHECKSUM 0x7f 468 469 /* DP_MAX_LANE_COUNT */ 470 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 471 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 472 473 /* DP_LANE_COUNT_SET */ 474 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 475 476 /* DP_TRAINING_LANE0_SET */ 477 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 478 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 479 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 480 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 481 482 enum link_lane_count_type { 483 LANE_COUNT1 = 1, 484 LANE_COUNT2 = 2, 485 LANE_COUNT4 = 4 486 }; 487 488 enum link_training_state { 489 START, 490 CLOCK_RECOVERY, 491 EQUALIZER_TRAINING, 492 FINISHED, 493 FAILED 494 }; 495 496 enum voltage_swing_level { 497 VOLTAGE_LEVEL_0, 498 VOLTAGE_LEVEL_1, 499 VOLTAGE_LEVEL_2, 500 VOLTAGE_LEVEL_3, 501 }; 502 503 enum pre_emphasis_level { 504 PRE_EMPHASIS_LEVEL_0, 505 PRE_EMPHASIS_LEVEL_1, 506 PRE_EMPHASIS_LEVEL_2, 507 PRE_EMPHASIS_LEVEL_3, 508 }; 509 510 enum pattern_set { 511 PRBS7, 512 D10_2, 513 TRAINING_PTN1, 514 TRAINING_PTN2, 515 TRAINING_PTN3, 516 DP_NONE 517 }; 518 519 enum color_space { 520 COLOR_RGB, 521 COLOR_YCBCR422, 522 COLOR_YCBCR444 523 }; 524 525 enum color_depth { 526 COLOR_6, 527 COLOR_8, 528 COLOR_10, 529 COLOR_12 530 }; 531 532 enum color_coefficient { 533 COLOR_YCBCR601, 534 COLOR_YCBCR709 535 }; 536 537 enum dynamic_range { 538 VESA, 539 CEA 540 }; 541 542 enum pll_status { 543 PLL_UNLOCKED, 544 PLL_LOCKED 545 }; 546 547 enum clock_recovery_m_value_type { 548 CALCULATED_M, 549 REGISTER_M 550 }; 551 552 enum video_timing_recognition_type { 553 VIDEO_TIMING_FROM_CAPTURE, 554 VIDEO_TIMING_FROM_REGISTER 555 }; 556 557 enum analog_power_block { 558 AUX_BLOCK, 559 CH0_BLOCK, 560 CH1_BLOCK, 561 CH2_BLOCK, 562 CH3_BLOCK, 563 ANALOG_TOTAL, 564 POWER_ALL 565 }; 566 567 enum dp_irq_type { 568 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 569 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 570 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 571 DP_IRQ_TYPE_UNKNOWN = BIT(3), 572 }; 573 574 struct video_info { 575 char *name; 576 577 bool h_sync_polarity; 578 bool v_sync_polarity; 579 bool interlaced; 580 581 enum color_space color_space; 582 enum dynamic_range dynamic_range; 583 enum color_coefficient ycbcr_coeff; 584 enum color_depth color_depth; 585 586 int max_link_rate; 587 enum link_lane_count_type max_lane_count; 588 }; 589 590 struct link_train { 591 int eq_loop; 592 int cr_loop[4]; 593 594 u8 link_rate; 595 u8 lane_count; 596 u8 training_lane[4]; 597 bool ssc; 598 599 enum link_training_state lt_state; 600 }; 601 602 enum analogix_dp_devtype { 603 EXYNOS_DP, 604 ROCKCHIP_DP, 605 }; 606 607 enum analogix_dp_sub_devtype { 608 RK3288_DP, 609 RK3368_EDP, 610 RK3399_EDP, 611 RK3568_EDP, 612 RK3588_EDP 613 }; 614 615 struct analogix_dp_plat_data { 616 enum analogix_dp_devtype dev_type; 617 enum analogix_dp_sub_devtype subdev_type; 618 bool ssc; 619 }; 620 621 struct analogix_dp_device { 622 int id; 623 struct udevice *dev; 624 void *reg_base; 625 struct regmap *grf; 626 struct phy phy; 627 struct reset_ctl_bulk resets; 628 struct gpio_desc hpd_gpio; 629 bool force_hpd; 630 struct video_info video_info; 631 struct link_train link_train; 632 struct drm_display_mode *mode; 633 struct analogix_dp_plat_data plat_data; 634 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 635 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 636 bool video_bist_enable; 637 u32 lane_map[4]; 638 }; 639 640 /* analogix_dp_reg.c */ 641 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 642 void analogix_dp_stop_video(struct analogix_dp_device *dp); 643 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 644 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 645 void analogix_dp_reset(struct analogix_dp_device *dp); 646 void analogix_dp_swreset(struct analogix_dp_device *dp); 647 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 648 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 649 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 650 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 651 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 652 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 653 enum analog_power_block block, 654 bool enable); 655 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 656 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 657 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 658 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 659 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 660 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 661 void analogix_dp_init_aux(struct analogix_dp_device *dp); 662 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 663 int analogix_dp_detect(struct analogix_dp_device *dp); 664 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 665 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 666 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 667 unsigned int reg_addr, 668 unsigned char data); 669 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 670 unsigned int reg_addr, 671 unsigned char *data); 672 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 673 unsigned int reg_addr, 674 unsigned int count, 675 unsigned char data[]); 676 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 677 unsigned int reg_addr, 678 unsigned int count, 679 unsigned char data[]); 680 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 681 unsigned int device_addr, 682 unsigned int reg_addr); 683 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 684 unsigned int device_addr, 685 unsigned int reg_addr, 686 unsigned int *data); 687 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 688 unsigned int device_addr, 689 unsigned int reg_addr, 690 unsigned int count, 691 unsigned char edid[]); 692 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 693 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 694 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 695 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 696 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 697 bool enable); 698 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 699 enum pattern_set pattern); 700 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 701 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 702 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 703 void analogix_dp_init_video(struct analogix_dp_device *dp); 704 705 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 706 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 707 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 708 enum clock_recovery_m_value_type type, 709 u32 m_value, 710 u32 n_value); 711 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 712 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 713 bool enable); 714 void analogix_dp_start_video(struct analogix_dp_device *dp); 715 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 716 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 717 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 718 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 719 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 720 void analogix_dp_set_video_format(struct analogix_dp_device *dp, 721 const struct drm_display_mode *mode); 722 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp); 723 724 #endif /* __DRM_ANALOGIX_DP__ */ 725