usb: dwc3: Disable suspend usb2 phy for rockchip platform

The rockchip SoCs need to disable usb2 phy enter suspend
mode which depends on the dwc3 suspend condition, otherwise
the usb2 phy doesn't ge

usb: dwc3: Disable suspend usb2 phy for rockchip platform

The rockchip SoCs need to disable usb2 phy enter suspend
mode which depends on the dwc3 suspend condition, otherwise
the usb2 phy doesn't get out of suspend and cause U-Boot
panic with the following log when scan some udisks.

XHCI timeout on event type 33... cannot recover.
BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()!
BUG!

Change-Id: I54e5e1bafc93ebac4ce4076d6a60bf1e5d36ef3d
Signed-off-by: William Wu <william.wu@rock-chips.com>

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usb: rockusb: Add support for usb3 download

This patch improve the usb gadget drivers and the usb
dwc3 controller drivers to support rockusb usb3 download
images.

With this patch, it can support:
1

usb: rockusb: Add support for usb3 download

This patch improve the usb gadget drivers and the usb
dwc3 controller drivers to support rockusb usb3 download
images.

With this patch, it can support:
1. Maskrom usbplug usb2 switch to usb3 automatically
if the boards and the upgrade tool support usb3.

2. Loader enter usb3 automatically if the boards support usb3.

3. Force Maskrom/Loader usb fall back to usb2 if wait
for usb3 enumeration time out.

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: william.wu <william.wu@rock-chips.com>
Change-Id: I9ad13fb42ae59cc9075545e22627f237f0eb1f32

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usb: dwc3: disable usb3 phy entering suspend mode

For some Rokchip SoCs like RK3588, if the USB3 PHY enters suspend mode
in U-Boot would cause the PHY initialize abortively in Linux Kernel.
So disab

usb: dwc3: disable usb3 phy entering suspend mode

For some Rokchip SoCs like RK3588, if the USB3 PHY enters suspend mode
in U-Boot would cause the PHY initialize abortively in Linux Kernel.
So disable the DWC3_GUSB3PIPECTL_SUSPHY feature in dwc3 core init
process to fix it.

Change-Id: I14d9446c7d6b408544a05ad3a70a63ed3318564e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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usb: dwc3: do not use 3.0 clock when operating in 2.0 mode

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the int

usb: dwc3: do not use 3.0 clock when operating in 2.0 mode

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>

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Merge branch 'next-dev' into thunder-boot

usb: dwc3: amend UTMI/UTMIW phy interface setup

Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Change-Id: I7

usb: dwc3: amend UTMI/UTMIW phy interface setup

Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Change-Id: I7fe45af396098749b2acf4a885dff875dcbc6f63
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when

usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Change-Id: Id90ac25a7e82bbf7918cc9658797c23008871852
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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usb: dwc3: add dis_enblslpm_quirk

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("us

usb: dwc3: add dis_enblslpm_quirk

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.

Change-Id: If8bffb5a8dc1b02e4b3100dc722d14a3d9b74992
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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usb: dwc3: add dis-u1u2-quirk to reject enter U1 and U2

The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC

usb: dwc3: add dis-u1u2-quirk to reject enter U1 and U2

The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC3 work as peripheral mode. This patch
adds a quirk to reject transition to U1 and U2 state to
workaround this issue.

Refer to commit aaa5c055cc06 ("usb: dwc3: add dis-u1u2-quirk to
reject enter U1 and U2") in Rockchip Linux Kernel-4.4 .

Change-Id: I1f4176caab3ccdc31ba7eb06684267833bf804db
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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Revert "UPSTREAM: drivers: usb: dwc3: setup phy before dwc3 core soft reset"

This reverts commit 0dcb583e26b1f519ecb0d8bbd997a710593be7e7.

Change-Id: If0f661a4e1b139c0d12b80e5fd98398bf0892373
Signe

Revert "UPSTREAM: drivers: usb: dwc3: setup phy before dwc3 core soft reset"

This reverts commit 0dcb583e26b1f519ecb0d8bbd997a710593be7e7.

Change-Id: If0f661a4e1b139c0d12b80e5fd98398bf0892373
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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UPSTREAM: usb: dwc3: Fix UTMI/UTMIW phy interface initialization

DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type

UPSTREAM: usb: dwc3: Fix UTMI/UTMIW phy interface initialization

DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.

The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.

So, handle the phy masking bits accordingly on respective interface
type cases.

Conflicts:
drivers/usb/dwc3/core.h

Change-Id: I28ce66d68984e30fa308a0b5a52c321d7bd96eda
Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 5c207282f53f86ecbf8c25cb691030d8c643ba1c)

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UPSTREAM: usb: dwc3: Add phy interface for dwc3_uboot

U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
call the dwc3_init in c

UPSTREAM: usb: dwc3: Add phy interface for dwc3_uboot

U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
call the dwc3_init in core.
- with non-dm variant gadget, so the usage board file would
call dwc3_uboot_init in core.

The driver probe would handle all respective gadget properties
including phy interface via phy_type property and then trigger
dwc3_init for dm-variant gadgets.

So, to support the phy interface for non-dm variant gadgets,
the better option is dwc3_uboot_init since there is no
dedicated controller for non-dm variant gadgets.

This patch support for adding phy interface like 8/16-bit UTMI+
code for dwc3_uboot.

This change used Linux phy.h enum list, to make proper code
compatibility.

Conflicts:
drivers/usb/dwc3/core.h

Change-Id: I626e2428b548a2624fead5418ecb8f7571c77e89
Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 6b7ebff00190649d2136b34f6feebc0dbe85bfdc)

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UPSTREAM: usb: dwc3: Add dwc3_of_parse() to get quirks information from DT

Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their ow

UPSTREAM: usb: dwc3: Add dwc3_of_parse() to get quirks information from DT

Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.

Change-Id: I0716519c36b390cee532d3556e136012a277d036
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ba6c5f7a28c8f8ac9eae194c2d37afa0ef51cb3d)

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UPSTREAM: usb: dwc3-generic: add a new host driver that uses the dwc3 core

Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core

UPSTREAM: usb: dwc3-generic: add a new host driver that uses the dwc3 core

Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".

In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.

Change-Id: I68b9e506836292d5de24feb55c5619d907c173ef
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b575e909168ca559609f6793720c4811b1dd55fd)

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UPSTREAM: usb: dwc3: switch to peripheral mode when exiting

This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be tur

UPSTREAM: usb: dwc3: switch to peripheral mode when exiting

This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.

Change-Id: Id674a95ff3cacb9e614cdc583f4a755e8301b7d7
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit bbe3d4a6c14e17d251029e4dde07f184244e9a4a)

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UPSTREAM: drivers: usb: dwc3: setup phy before dwc3 core soft reset

Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host

UPSTREAM: drivers: usb: dwc3: setup phy before dwc3 core soft reset

Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host side.

Change-Id: I4e49d99544d0cd4a6c4215652b9ca328d29ce24c
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1a031d236a9eeb28ced5438242987ae6a45f3054)

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UPSTREAM: dwc3: move phy operation to core.c

Those operations can be used for peripheral operation as well as host
operation.

Change-Id: Ifa3b83bd690cd11f6750fd893e6ac36b2a0214b3
Signed-off-by: Jea

UPSTREAM: dwc3: move phy operation to core.c

Those operations can be used for peripheral operation as well as host
operation.

Change-Id: Ifa3b83bd690cd11f6750fd893e6ac36b2a0214b3
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit d648a50c0a27452a5439e7982b23b97c64820430)

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UPSTREAM: usb: introduce a separate config option for DM USB device

Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.

Conflicts:
arch/arm/Kconfig

Change-Id:

UPSTREAM: usb: introduce a separate config option for DM USB device

Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.

Conflicts:
arch/arm/Kconfig

Change-Id: I075c887a77e2243463a580eac59d842b620af2f5
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 687ab54560809e01a10652ef82dbac6ae72deb91)

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UPSTREAM: usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/

This allows to disable the USB driver model in SPL because it checks
the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for
regu

UPSTREAM: usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/

This allows to disable the USB driver model in SPL because it checks
the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for
regular non-SPL builds.

Conflicts:
drivers/usb/host/ehci-atmel.c
drivers/usb/host/xhci-fsl.c

Change-Id: If6c980c620cf97c1dd131f60953c305e34dba505
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit fd09c205fc57b90a782cac33449ef172575d0a8c)

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UPSTREAM: usb: dwc3: Add dwc3_init/remove with DM_USB

The patch is preparing dwc3 core for enabling DM_USB with peripheral
driver with using driver model support.
The driver will be bound by the DWC

UPSTREAM: usb: dwc3: Add dwc3_init/remove with DM_USB

The patch is preparing dwc3 core for enabling DM_USB with peripheral
driver with using driver model support.
The driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.

Change-Id: If18bda57dfccaa3df104df5defa326d930a8abbe
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
(Remove dwc3-omap changes)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 23ba2d6372e45479106922c6241a7a09707bbe08)

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UPSTREAM: drivers: usb: dwc3: remove devm_zalloc from linux_compact

devm_zalloc() is already defined in dm/device.h header, so
devm_zalloc can be removed from linux_compact.h beader file.

Change-Id

UPSTREAM: drivers: usb: dwc3: remove devm_zalloc from linux_compact

devm_zalloc() is already defined in dm/device.h header, so
devm_zalloc can be removed from linux_compact.h beader file.

Change-Id: I33e25cbd18245d689d4599ef2a1e46603128c633
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 0ad3f771b69c0db837f40f6ffd5d41915fc07095)

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usb: dwc3: init phy utmi width in platform data

On rk3399 board, we need to configure phy interface UTMI+ width
to 16 bits via the property "snps,phyif-utmi-bits" of dwc3 node.
But we can't the get

usb: dwc3: init phy utmi width in platform data

On rk3399 board, we need to configure phy interface UTMI+ width
to 16 bits via the property "snps,phyif-utmi-bits" of dwc3 node.
But we can't the get the property from kernel dtb. So this patch
initialize the phy interface UTMI+ width in dwc3 platform data,
and not dependent on the property in dtb.

Change-Id: I3f6b05e0d72806242a128c85f82b260f61ac4f95
Signed-off-by: William Wu <william.wu@rock-chips.com>

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FROMLIST: usb: dwc3: add support for 16 bit UTMI+ interface

The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one variable in dwc3/dwc3_device struct to support 16 bit
UTMI+ int

FROMLIST: usb: dwc3: add support for 16 bit UTMI+ interface

The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one variable in dwc3/dwc3_device struct to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.

Change-Id: Ic5db5e9ee845b5f9d2848bb44fbf07c094b3b5a7
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-usb

usb: dwc3: gadget: make cache-maintenance on event buffers more robust

Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.

usb: dwc3: gadget: make cache-maintenance on event buffers more robust

Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).

The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
# during initialisation:
1. allocate buffers via memalign
=> buffers may still be modified (cached, dirty)
# during interrupt processing
2. clean + invalidate buffers
=> may commit stale data from a modified cacheline
3. read from buffers

This could lead to garbage info being written to buffers before
reading them during even-processing.

To make the event processing more robust, we use the following sequence
for the cache-maintenance:
# during initialisation:
1. allocate buffers via memalign
2. clean + invalidate buffers
(we only need the 'invalidate' part, but dwc3_flush_cache()
always performs a 'clean + invalidate')
# during interrupt processing
3. read the buffers
(we know these lines are not cached, due to the previous
invalidation and no other code touching them in-between)
4. clean + invalidate buffers
=> writes back any modification we may have made during event
processing and ensures that the lines are not in the cache
the next time we enter interrupt processing

Note that with the original sequence, we observe reproducible
(depending on the cache state: i.e. running dhcp/usb start before will
upset caches to get us around this) issues in the event processing (a
fatal synchronous abort in dwc3_gadget_uboot_handle_interrupt on the
first time interrupt handling is invoked) when running USB mass
storage emulation on our RK3399-Q7 with data-caches on.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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