1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 #include <generic-phy.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static LIST_HEAD(dwc3_list); 37 /* -------------------------------------------------------------------------- */ 38 39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 40 { 41 u32 reg; 42 43 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 45 reg |= DWC3_GCTL_PRTCAPDIR(mode); 46 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 47 } 48 49 /** 50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_core_soft_reset(struct dwc3 *dwc) 54 { 55 u32 reg; 56 57 /* Before Resetting PHY, put Core in Reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 59 reg |= DWC3_GCTL_CORESOFTRESET; 60 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 61 62 /* Assert USB3 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 66 67 /* Assert USB2 PHY reset */ 68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 71 72 mdelay(100); 73 74 /* Clear USB3 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 78 79 /* Clear USB2 PHY reset */ 80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 83 84 mdelay(100); 85 86 /* After PHYs are stable we can take Core out of reset state */ 87 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 88 reg &= ~DWC3_GCTL_CORESOFTRESET; 89 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 90 91 return 0; 92 } 93 94 /** 95 * dwc3_free_one_event_buffer - Frees one event buffer 96 * @dwc: Pointer to our controller context structure 97 * @evt: Pointer to event buffer to be freed 98 */ 99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 100 struct dwc3_event_buffer *evt) 101 { 102 dma_free_coherent(evt->buf); 103 } 104 105 /** 106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 107 * @dwc: Pointer to our controller context structure 108 * @length: size of the event buffer 109 * 110 * Returns a pointer to the allocated event buffer structure on success 111 * otherwise ERR_PTR(errno). 112 */ 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 114 unsigned length) 115 { 116 struct dwc3_event_buffer *evt; 117 118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 119 GFP_KERNEL); 120 if (!evt) 121 return ERR_PTR(-ENOMEM); 122 123 evt->dwc = dwc; 124 evt->length = length; 125 evt->buf = dma_alloc_coherent(length, 126 (unsigned long *)&evt->dma); 127 if (!evt->buf) 128 return ERR_PTR(-ENOMEM); 129 130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 131 132 return evt; 133 } 134 135 /** 136 * dwc3_free_event_buffers - frees all allocated event buffers 137 * @dwc: Pointer to our controller context structure 138 */ 139 static void dwc3_free_event_buffers(struct dwc3 *dwc) 140 { 141 struct dwc3_event_buffer *evt; 142 int i; 143 144 for (i = 0; i < dwc->num_event_buffers; i++) { 145 evt = dwc->ev_buffs[i]; 146 if (evt) 147 dwc3_free_one_event_buffer(dwc, evt); 148 } 149 } 150 151 /** 152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 153 * @dwc: pointer to our controller context structure 154 * @length: size of event buffer 155 * 156 * Returns 0 on success otherwise negative errno. In the error case, dwc 157 * may contain some buffers allocated but not all which were requested. 158 */ 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 160 { 161 int num; 162 int i; 163 164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 165 dwc->num_event_buffers = num; 166 167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 168 sizeof(*dwc->ev_buffs) * num); 169 if (!dwc->ev_buffs) 170 return -ENOMEM; 171 172 for (i = 0; i < num; i++) { 173 struct dwc3_event_buffer *evt; 174 175 evt = dwc3_alloc_one_event_buffer(dwc, length); 176 if (IS_ERR(evt)) { 177 dev_err(dwc->dev, "can't allocate event buffer\n"); 178 return PTR_ERR(evt); 179 } 180 dwc->ev_buffs[i] = evt; 181 } 182 183 return 0; 184 } 185 186 /** 187 * dwc3_event_buffers_setup - setup our allocated event buffers 188 * @dwc: pointer to our controller context structure 189 * 190 * Returns 0 on success otherwise negative errno. 191 */ 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 193 { 194 struct dwc3_event_buffer *evt; 195 int n; 196 197 for (n = 0; n < dwc->num_event_buffers; n++) { 198 evt = dwc->ev_buffs[n]; 199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 200 evt->buf, (unsigned long long) evt->dma, 201 evt->length); 202 203 evt->lpos = 0; 204 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 206 lower_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 208 upper_32_bits(evt->dma)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 210 DWC3_GEVNTSIZ_SIZE(evt->length)); 211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 212 } 213 214 return 0; 215 } 216 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 218 { 219 struct dwc3_event_buffer *evt; 220 int n; 221 222 for (n = 0; n < dwc->num_event_buffers; n++) { 223 evt = dwc->ev_buffs[n]; 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 230 | DWC3_GEVNTSIZ_SIZE(0)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 232 } 233 } 234 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 236 { 237 if (!dwc->has_hibernation) 238 return 0; 239 240 if (!dwc->nr_scratch) 241 return 0; 242 243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 245 if (!dwc->scratchbuf) 246 return -ENOMEM; 247 248 return 0; 249 } 250 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 252 { 253 dma_addr_t scratch_addr; 254 u32 param; 255 int ret; 256 257 if (!dwc->has_hibernation) 258 return 0; 259 260 if (!dwc->nr_scratch) 261 return 0; 262 263 scratch_addr = dma_map_single(dwc->scratchbuf, 264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 265 DMA_BIDIRECTIONAL); 266 if (dma_mapping_error(dwc->dev, scratch_addr)) { 267 dev_err(dwc->dev, "failed to map scratch buffer\n"); 268 ret = -EFAULT; 269 goto err0; 270 } 271 272 dwc->scratch_addr = scratch_addr; 273 274 param = lower_32_bits(scratch_addr); 275 276 ret = dwc3_send_gadget_generic_command(dwc, 277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 278 if (ret < 0) 279 goto err1; 280 281 param = upper_32_bits(scratch_addr); 282 283 ret = dwc3_send_gadget_generic_command(dwc, 284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 285 if (ret < 0) 286 goto err1; 287 288 return 0; 289 290 err1: 291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 293 294 err0: 295 return ret; 296 } 297 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 299 { 300 if (!dwc->has_hibernation) 301 return; 302 303 if (!dwc->nr_scratch) 304 return; 305 306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 308 kfree(dwc->scratchbuf); 309 } 310 311 static void dwc3_core_num_eps(struct dwc3 *dwc) 312 { 313 struct dwc3_hwparams *parms = &dwc->hwparams; 314 315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 317 318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 319 dwc->num_in_eps, dwc->num_out_eps); 320 } 321 322 static void dwc3_cache_hwparams(struct dwc3 *dwc) 323 { 324 struct dwc3_hwparams *parms = &dwc->hwparams; 325 326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 335 } 336 337 /** 338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 339 * @dwc: Pointer to our controller context structure 340 */ 341 static void dwc3_phy_setup(struct dwc3 *dwc) 342 { 343 u32 reg; 344 345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 346 347 /* 348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 349 * to '0' during coreConsultant configuration. So default value 350 * will be '0' when the core is reset. Application needs to set it 351 * to '1' after the core initialization is completed. 352 */ 353 if (dwc->revision > DWC3_REVISION_194A) 354 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 355 356 if (dwc->u2ss_inp3_quirk) 357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 358 359 if (dwc->req_p1p2p3_quirk) 360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 361 362 if (dwc->del_p1p2p3_quirk) 363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 364 365 if (dwc->del_phy_power_chg_quirk) 366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 367 368 if (dwc->lfps_filter_quirk) 369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 370 371 if (dwc->rx_detect_poll_quirk) 372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 373 374 if (dwc->tx_de_emphasis_quirk) 375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 376 377 if (dwc->dis_u3_susphy_quirk) 378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 379 380 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 381 382 mdelay(100); 383 384 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 385 386 /* 387 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 388 * '0' during coreConsultant configuration. So default value will 389 * be '0' when the core is reset. Application needs to set it to 390 * '1' after the core initialization is completed. 391 */ 392 if (dwc->revision > DWC3_REVISION_194A) 393 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 394 395 if (dwc->dis_u2_susphy_quirk) 396 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 397 398 if (dwc->dis_enblslpm_quirk) 399 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 400 401 if (dwc->usb2_phyif_utmi_width == 16) { 402 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 403 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 404 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 405 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT); 406 } 407 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 408 409 mdelay(100); 410 } 411 412 /** 413 * dwc3_core_init - Low-level initialization of DWC3 Core 414 * @dwc: Pointer to our controller context structure 415 * 416 * Returns 0 on success otherwise negative errno. 417 */ 418 static int dwc3_core_init(struct dwc3 *dwc) 419 { 420 unsigned long timeout; 421 u32 hwparams4 = dwc->hwparams.hwparams4; 422 u32 reg; 423 int ret; 424 425 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 426 /* This should read as U3 followed by revision number */ 427 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 428 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 429 ret = -ENODEV; 430 goto err0; 431 } 432 dwc->revision = reg; 433 434 /* Handle USB2.0-only core configuration */ 435 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 436 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 437 if (dwc->maximum_speed == USB_SPEED_SUPER) 438 dwc->maximum_speed = USB_SPEED_HIGH; 439 } 440 441 /* issue device SoftReset too */ 442 timeout = 5000; 443 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 444 while (timeout--) { 445 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 446 if (!(reg & DWC3_DCTL_CSFTRST)) 447 break; 448 }; 449 450 if (!timeout) { 451 dev_err(dwc->dev, "Reset Timed Out\n"); 452 ret = -ETIMEDOUT; 453 goto err0; 454 } 455 456 ret = dwc3_core_soft_reset(dwc); 457 if (ret) 458 goto err0; 459 460 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 461 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 462 463 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 464 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 465 /** 466 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 467 * issue which would cause xHCI compliance tests to fail. 468 * 469 * Because of that we cannot enable clock gating on such 470 * configurations. 471 * 472 * Refers to: 473 * 474 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 475 * SOF/ITP Mode Used 476 */ 477 if ((dwc->dr_mode == USB_DR_MODE_HOST || 478 dwc->dr_mode == USB_DR_MODE_OTG) && 479 (dwc->revision >= DWC3_REVISION_210A && 480 dwc->revision <= DWC3_REVISION_250A)) 481 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 482 else 483 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 484 break; 485 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 486 /* enable hibernation here */ 487 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 488 489 /* 490 * REVISIT Enabling this bit so that host-mode hibernation 491 * will work. Device-mode hibernation is not yet implemented. 492 */ 493 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 494 break; 495 default: 496 dev_dbg(dwc->dev, "No power optimization available\n"); 497 } 498 499 /* check if current dwc3 is on simulation board */ 500 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 501 dev_dbg(dwc->dev, "it is on FPGA board\n"); 502 dwc->is_fpga = true; 503 } 504 505 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 506 WARN(true, 507 "disable_scramble cannot be used on non-FPGA builds\n"); 508 509 if (dwc->disable_scramble_quirk && dwc->is_fpga) 510 reg |= DWC3_GCTL_DISSCRAMBLE; 511 else 512 reg &= ~DWC3_GCTL_DISSCRAMBLE; 513 514 if (dwc->u2exit_lfps_quirk) 515 reg |= DWC3_GCTL_U2EXIT_LFPS; 516 517 /* 518 * WORKAROUND: DWC3 revisions <1.90a have a bug 519 * where the device can fail to connect at SuperSpeed 520 * and falls back to high-speed mode which causes 521 * the device to enter a Connect/Disconnect loop 522 */ 523 if (dwc->revision < DWC3_REVISION_190A) 524 reg |= DWC3_GCTL_U2RSTECN; 525 526 dwc3_core_num_eps(dwc); 527 528 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 529 530 dwc3_phy_setup(dwc); 531 532 ret = dwc3_alloc_scratch_buffers(dwc); 533 if (ret) 534 goto err0; 535 536 ret = dwc3_setup_scratch_buffers(dwc); 537 if (ret) 538 goto err1; 539 540 return 0; 541 542 err1: 543 dwc3_free_scratch_buffers(dwc); 544 545 err0: 546 return ret; 547 } 548 549 static void dwc3_core_exit(struct dwc3 *dwc) 550 { 551 dwc3_free_scratch_buffers(dwc); 552 } 553 554 static int dwc3_core_init_mode(struct dwc3 *dwc) 555 { 556 int ret; 557 558 switch (dwc->dr_mode) { 559 case USB_DR_MODE_PERIPHERAL: 560 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 561 ret = dwc3_gadget_init(dwc); 562 if (ret) { 563 dev_err(dev, "failed to initialize gadget\n"); 564 return ret; 565 } 566 break; 567 case USB_DR_MODE_HOST: 568 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 569 ret = dwc3_host_init(dwc); 570 if (ret) { 571 dev_err(dev, "failed to initialize host\n"); 572 return ret; 573 } 574 break; 575 case USB_DR_MODE_OTG: 576 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 577 ret = dwc3_host_init(dwc); 578 if (ret) { 579 dev_err(dev, "failed to initialize host\n"); 580 return ret; 581 } 582 583 ret = dwc3_gadget_init(dwc); 584 if (ret) { 585 dev_err(dev, "failed to initialize gadget\n"); 586 return ret; 587 } 588 break; 589 default: 590 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 591 return -EINVAL; 592 } 593 594 return 0; 595 } 596 597 static void dwc3_gadget_run(struct dwc3 *dwc) 598 { 599 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); 600 mdelay(100); 601 } 602 603 static void dwc3_core_exit_mode(struct dwc3 *dwc) 604 { 605 switch (dwc->dr_mode) { 606 case USB_DR_MODE_PERIPHERAL: 607 dwc3_gadget_exit(dwc); 608 break; 609 case USB_DR_MODE_HOST: 610 dwc3_host_exit(dwc); 611 break; 612 case USB_DR_MODE_OTG: 613 dwc3_host_exit(dwc); 614 dwc3_gadget_exit(dwc); 615 break; 616 default: 617 /* do nothing */ 618 break; 619 } 620 621 /* 622 * switch back to peripheral mode 623 * This enables the phy to enter idle and then, if enabled, suspend. 624 */ 625 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 626 dwc3_gadget_run(dwc); 627 } 628 629 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, 630 struct dwc3 *dwc) 631 { 632 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode; 633 u32 reg; 634 635 /* Set dwc3 usb2 phy config */ 636 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 637 638 switch (hsphy_mode) { 639 case USBPHY_INTERFACE_MODE_UTMI: 640 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 641 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 642 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 643 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 644 break; 645 case USBPHY_INTERFACE_MODE_UTMIW: 646 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 647 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 648 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 649 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 650 break; 651 default: 652 break; 653 } 654 655 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 656 } 657 658 #define DWC3_ALIGN_MASK (16 - 1) 659 660 /** 661 * dwc3_uboot_init - dwc3 core uboot initialization code 662 * @dwc3_dev: struct dwc3_device containing initialization data 663 * 664 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 665 * kernel driver). Pointer to dwc3_device should be passed containing 666 * base address and other initialization data. Returns '0' on success and 667 * a negative value on failure. 668 * 669 * Generally called from board_usb_init() implemented in board file. 670 */ 671 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 672 { 673 struct dwc3 *dwc; 674 struct device *dev = NULL; 675 u8 lpm_nyet_threshold; 676 u8 tx_de_emphasis; 677 u8 hird_threshold; 678 679 int ret; 680 681 void *mem; 682 const void *blob = gd->fdt_blob; 683 int node; 684 685 mem = devm_kzalloc((struct udevice *)dev, 686 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 687 if (!mem) 688 return -ENOMEM; 689 690 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 691 dwc->mem = mem; 692 693 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 694 DWC3_GLOBALS_REGS_START); 695 696 /* default to highest possible threshold */ 697 lpm_nyet_threshold = 0xff; 698 699 /* default to -3.5dB de-emphasis */ 700 tx_de_emphasis = 1; 701 702 /* 703 * default to assert utmi_sleep_n and use maximum allowed HIRD 704 * threshold value of 0b1100 705 */ 706 hird_threshold = 12; 707 708 dwc->maximum_speed = dwc3_dev->maximum_speed; 709 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 710 if (dwc3_dev->lpm_nyet_threshold) 711 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 712 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 713 if (dwc3_dev->hird_threshold) 714 hird_threshold = dwc3_dev->hird_threshold; 715 716 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 717 dwc->dr_mode = dwc3_dev->dr_mode; 718 719 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 720 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 721 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 722 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 723 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 724 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 725 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 726 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 727 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 728 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 729 dwc->dis_u1u2_quirk = dwc3_dev->dis_u2_susphy_quirk; 730 731 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 732 if (dwc3_dev->tx_de_emphasis) 733 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 734 735 /* default to superspeed if no maximum_speed passed */ 736 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 737 dwc->maximum_speed = USB_SPEED_SUPER; 738 739 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 740 dwc->tx_de_emphasis = tx_de_emphasis; 741 742 dwc->hird_threshold = hird_threshold 743 | (dwc->is_utmi_l1_suspend << 4); 744 745 dwc->index = dwc3_dev->index; 746 747 if (dwc3_dev->usb2_phyif_utmi_width) 748 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 749 750 node = fdt_node_offset_by_compatible(blob, -1, 751 "rockchip,rk3399-xhci"); 752 if (node < 0) 753 debug("%s dwc3 node not found\n", __func__); 754 else 755 dwc->usb2_phyif_utmi_width = 756 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 757 758 dwc3_cache_hwparams(dwc); 759 760 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 761 if (ret) { 762 dev_err(dwc->dev, "failed to allocate event buffers\n"); 763 return -ENOMEM; 764 } 765 766 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 767 dwc->dr_mode = USB_DR_MODE_HOST; 768 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 769 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 770 771 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 772 dwc->dr_mode = USB_DR_MODE_OTG; 773 774 ret = dwc3_core_init(dwc); 775 if (ret) { 776 dev_err(dev, "failed to initialize core\n"); 777 goto err0; 778 } 779 780 dwc3_uboot_hsphy_mode(dwc3_dev, dwc); 781 782 ret = dwc3_event_buffers_setup(dwc); 783 if (ret) { 784 dev_err(dwc->dev, "failed to setup event buffers\n"); 785 goto err1; 786 } 787 788 ret = dwc3_core_init_mode(dwc); 789 if (ret) 790 goto err2; 791 792 list_add_tail(&dwc->list, &dwc3_list); 793 794 return 0; 795 796 err2: 797 dwc3_event_buffers_cleanup(dwc); 798 799 err1: 800 dwc3_core_exit(dwc); 801 802 err0: 803 dwc3_free_event_buffers(dwc); 804 805 return ret; 806 } 807 808 /** 809 * dwc3_uboot_exit - dwc3 core uboot cleanup code 810 * @index: index of this controller 811 * 812 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 813 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 814 * should be passed and should match with the index passed in 815 * dwc3_device during init. 816 * 817 * Generally called from board file. 818 */ 819 void dwc3_uboot_exit(int index) 820 { 821 struct dwc3 *dwc; 822 823 list_for_each_entry(dwc, &dwc3_list, list) { 824 if (dwc->index != index) 825 continue; 826 827 dwc3_core_exit_mode(dwc); 828 dwc3_event_buffers_cleanup(dwc); 829 dwc3_free_event_buffers(dwc); 830 dwc3_core_exit(dwc); 831 list_del(&dwc->list); 832 kfree(dwc->mem); 833 break; 834 } 835 } 836 837 /** 838 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 839 * @index: index of this controller 840 * 841 * Invokes dwc3 gadget interrupts. 842 * 843 * Generally called from board file. 844 */ 845 void dwc3_uboot_handle_interrupt(int index) 846 { 847 struct dwc3 *dwc = NULL; 848 849 list_for_each_entry(dwc, &dwc3_list, list) { 850 if (dwc->index != index) 851 continue; 852 853 dwc3_gadget_uboot_handle_interrupt(dwc); 854 break; 855 } 856 } 857 858 MODULE_ALIAS("platform:dwc3"); 859 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 860 MODULE_LICENSE("GPL v2"); 861 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 862 863 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) 864 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) 865 { 866 int i, ret, count; 867 struct phy *usb_phys; 868 869 /* Return if no phy declared */ 870 if (!dev_read_prop(dev, "phys", NULL)) 871 return 0; 872 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 873 if (count <= 0) 874 return count; 875 876 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 877 GFP_KERNEL); 878 if (!usb_phys) 879 return -ENOMEM; 880 881 for (i = 0; i < count; i++) { 882 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); 883 if (ret && ret != -ENOENT) { 884 pr_err("Failed to get USB PHY%d for %s\n", 885 i, dev->name); 886 return ret; 887 } 888 } 889 890 for (i = 0; i < count; i++) { 891 ret = generic_phy_init(&usb_phys[i]); 892 if (ret) { 893 pr_err("Can't init USB PHY%d for %s\n", 894 i, dev->name); 895 goto phys_init_err; 896 } 897 } 898 899 for (i = 0; i < count; i++) { 900 ret = generic_phy_power_on(&usb_phys[i]); 901 if (ret) { 902 pr_err("Can't power USB PHY%d for %s\n", 903 i, dev->name); 904 goto phys_poweron_err; 905 } 906 } 907 908 *array = usb_phys; 909 *num_phys = count; 910 return 0; 911 912 phys_poweron_err: 913 for (i = count - 1; i >= 0; i--) 914 generic_phy_power_off(&usb_phys[i]); 915 916 for (i = 0; i < count; i++) 917 generic_phy_exit(&usb_phys[i]); 918 919 return ret; 920 921 phys_init_err: 922 for (; i >= 0; i--) 923 generic_phy_exit(&usb_phys[i]); 924 925 return ret; 926 } 927 928 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) 929 { 930 int i, ret; 931 932 for (i = 0; i < num_phys; i++) { 933 if (!generic_phy_valid(&usb_phys[i])) 934 continue; 935 936 ret = generic_phy_power_off(&usb_phys[i]); 937 ret |= generic_phy_exit(&usb_phys[i]); 938 if (ret) { 939 pr_err("Can't shutdown USB PHY%d for %s\n", 940 i, dev->name); 941 } 942 } 943 944 return 0; 945 } 946 #endif 947 948 #if CONFIG_IS_ENABLED(DM_USB) 949 void dwc3_of_parse(struct dwc3 *dwc) 950 { 951 const u8 *tmp; 952 struct udevice *dev = dwc->dev; 953 u8 lpm_nyet_threshold; 954 u8 tx_de_emphasis; 955 u8 hird_threshold; 956 957 /* default to highest possible threshold */ 958 lpm_nyet_threshold = 0xff; 959 960 /* default to -3.5dB de-emphasis */ 961 tx_de_emphasis = 1; 962 963 /* 964 * default to assert utmi_sleep_n and use maximum allowed HIRD 965 * threshold value of 0b1100 966 */ 967 hird_threshold = 12; 968 969 dwc->has_lpm_erratum = dev_read_bool(dev, 970 "snps,has-lpm-erratum"); 971 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); 972 if (tmp) 973 lpm_nyet_threshold = *tmp; 974 975 dwc->is_utmi_l1_suspend = dev_read_bool(dev, 976 "snps,is-utmi-l1-suspend"); 977 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); 978 if (tmp) 979 hird_threshold = *tmp; 980 981 dwc->disable_scramble_quirk = dev_read_bool(dev, 982 "snps,disable_scramble_quirk"); 983 dwc->u2exit_lfps_quirk = dev_read_bool(dev, 984 "snps,u2exit_lfps_quirk"); 985 dwc->u2ss_inp3_quirk = dev_read_bool(dev, 986 "snps,u2ss_inp3_quirk"); 987 dwc->req_p1p2p3_quirk = dev_read_bool(dev, 988 "snps,req_p1p2p3_quirk"); 989 dwc->del_p1p2p3_quirk = dev_read_bool(dev, 990 "snps,del_p1p2p3_quirk"); 991 dwc->del_phy_power_chg_quirk = dev_read_bool(dev, 992 "snps,del_phy_power_chg_quirk"); 993 dwc->lfps_filter_quirk = dev_read_bool(dev, 994 "snps,lfps_filter_quirk"); 995 dwc->rx_detect_poll_quirk = dev_read_bool(dev, 996 "snps,rx_detect_poll_quirk"); 997 dwc->dis_u3_susphy_quirk = dev_read_bool(dev, 998 "snps,dis_u3_susphy_quirk"); 999 dwc->dis_u2_susphy_quirk = dev_read_bool(dev, 1000 "snps,dis_u2_susphy_quirk"); 1001 dwc->dis_enblslpm_quirk = dev_read_bool(dev, 1002 "snps,dis_enblslpm_quirk"); 1003 dwc->tx_de_emphasis_quirk = dev_read_bool(dev, 1004 "snps,tx_de_emphasis_quirk"); 1005 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); 1006 if (tmp) 1007 tx_de_emphasis = *tmp; 1008 1009 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1010 dwc->tx_de_emphasis = tx_de_emphasis; 1011 1012 dwc->hird_threshold = hird_threshold 1013 | (dwc->is_utmi_l1_suspend << 4); 1014 } 1015 1016 int dwc3_init(struct dwc3 *dwc) 1017 { 1018 int ret; 1019 1020 dwc3_cache_hwparams(dwc); 1021 1022 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1023 if (ret) { 1024 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1025 return -ENOMEM; 1026 } 1027 1028 ret = dwc3_core_init(dwc); 1029 if (ret) { 1030 dev_err(dev, "failed to initialize core\n"); 1031 goto core_fail; 1032 } 1033 1034 ret = dwc3_event_buffers_setup(dwc); 1035 if (ret) { 1036 dev_err(dwc->dev, "failed to setup event buffers\n"); 1037 goto event_fail; 1038 } 1039 1040 ret = dwc3_core_init_mode(dwc); 1041 if (ret) 1042 goto mode_fail; 1043 1044 return 0; 1045 1046 mode_fail: 1047 dwc3_event_buffers_cleanup(dwc); 1048 1049 event_fail: 1050 dwc3_core_exit(dwc); 1051 1052 core_fail: 1053 dwc3_free_event_buffers(dwc); 1054 1055 return ret; 1056 } 1057 1058 void dwc3_remove(struct dwc3 *dwc) 1059 { 1060 dwc3_core_exit_mode(dwc); 1061 dwc3_event_buffers_cleanup(dwc); 1062 dwc3_free_event_buffers(dwc); 1063 dwc3_core_exit(dwc); 1064 kfree(dwc->mem); 1065 } 1066 #endif 1067