1 /* 2 * SH QSPI (Quad SPI) driver 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <console.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <wait_bit.h> 15 #include <asm/arch/rmobile.h> 16 #include <asm/io.h> 17 18 /* SH QSPI register bit masks <REG>_<BIT> */ 19 #define SPCR_MSTR 0x08 20 #define SPCR_SPE 0x40 21 #define SPSR_SPRFF 0x80 22 #define SPSR_SPTEF 0x20 23 #define SPPCR_IO3FV 0x04 24 #define SPPCR_IO2FV 0x02 25 #define SPPCR_IO1FV 0x01 26 #define SPBDCR_RXBC0 BIT(0) 27 #define SPCMD_SCKDEN BIT(15) 28 #define SPCMD_SLNDEN BIT(14) 29 #define SPCMD_SPNDEN BIT(13) 30 #define SPCMD_SSLKP BIT(7) 31 #define SPCMD_BRDV0 BIT(2) 32 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ 33 SPCMD_SPNDEN | SPCMD_SSLKP | \ 34 SPCMD_BRDV0 35 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ 36 SPCMD_BRDV0 37 #define SPBFCR_TXRST BIT(7) 38 #define SPBFCR_RXRST BIT(6) 39 40 /* SH QSPI register set */ 41 struct sh_qspi_regs { 42 u8 spcr; 43 u8 sslp; 44 u8 sppcr; 45 u8 spsr; 46 u32 spdr; 47 u8 spscr; 48 u8 spssr; 49 u8 spbr; 50 u8 spdcr; 51 u8 spckd; 52 u8 sslnd; 53 u8 spnd; 54 u8 dummy0; 55 u16 spcmd0; 56 u16 spcmd1; 57 u16 spcmd2; 58 u16 spcmd3; 59 u8 spbfcr; 60 u8 dummy1; 61 u16 spbdcr; 62 u32 spbmul0; 63 u32 spbmul1; 64 u32 spbmul2; 65 u32 spbmul3; 66 }; 67 68 struct sh_qspi_slave { 69 struct spi_slave slave; 70 struct sh_qspi_regs *regs; 71 }; 72 73 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) 74 { 75 return container_of(slave, struct sh_qspi_slave, slave); 76 } 77 78 static void sh_qspi_init(struct sh_qspi_slave *ss) 79 { 80 /* QSPI initialize */ 81 /* Set master mode only */ 82 writeb(SPCR_MSTR, &ss->regs->spcr); 83 84 /* Set SSL signal level */ 85 writeb(0x00, &ss->regs->sslp); 86 87 /* Set MOSI signal value when transfer is in idle state */ 88 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); 89 90 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ 91 writeb(0x01, &ss->regs->spbr); 92 93 /* Disable Dummy Data Transmission */ 94 writeb(0x00, &ss->regs->spdcr); 95 96 /* Set clock delay value */ 97 writeb(0x00, &ss->regs->spckd); 98 99 /* Set SSL negation delay value */ 100 writeb(0x00, &ss->regs->sslnd); 101 102 /* Set next-access delay value */ 103 writeb(0x00, &ss->regs->spnd); 104 105 /* Set equence command */ 106 writew(SPCMD_INIT2, &ss->regs->spcmd0); 107 108 /* Reset transfer and receive Buffer */ 109 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 110 111 /* Clear transfer and receive Buffer control bit */ 112 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 113 114 /* Set equence control method. Use equence0 only */ 115 writeb(0x00, &ss->regs->spscr); 116 117 /* Enable SPI function */ 118 setbits_8(&ss->regs->spcr, SPCR_SPE); 119 } 120 121 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 122 { 123 return 1; 124 } 125 126 void spi_cs_activate(struct spi_slave *slave) 127 { 128 struct sh_qspi_slave *ss = to_sh_qspi(slave); 129 130 /* Set master mode only */ 131 writeb(SPCR_MSTR, &ss->regs->spcr); 132 133 /* Set command */ 134 writew(SPCMD_INIT1, &ss->regs->spcmd0); 135 136 /* Reset transfer and receive Buffer */ 137 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 138 139 /* Clear transfer and receive Buffer control bit */ 140 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 141 142 /* Set equence control method. Use equence0 only */ 143 writeb(0x00, &ss->regs->spscr); 144 145 /* Enable SPI function */ 146 setbits_8(&ss->regs->spcr, SPCR_SPE); 147 } 148 149 void spi_cs_deactivate(struct spi_slave *slave) 150 { 151 struct sh_qspi_slave *ss = to_sh_qspi(slave); 152 153 /* Disable SPI Function */ 154 clrbits_8(&ss->regs->spcr, SPCR_SPE); 155 } 156 157 void spi_init(void) 158 { 159 /* nothing to do */ 160 } 161 162 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 163 unsigned int max_hz, unsigned int mode) 164 { 165 struct sh_qspi_slave *ss; 166 167 if (!spi_cs_is_valid(bus, cs)) 168 return NULL; 169 170 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); 171 if (!ss) { 172 printf("SPI_error: Fail to allocate sh_qspi_slave\n"); 173 return NULL; 174 } 175 176 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE; 177 178 /* Init SH QSPI */ 179 sh_qspi_init(ss); 180 181 return &ss->slave; 182 } 183 184 void spi_free_slave(struct spi_slave *slave) 185 { 186 struct sh_qspi_slave *spi = to_sh_qspi(slave); 187 188 free(spi); 189 } 190 191 int spi_claim_bus(struct spi_slave *slave) 192 { 193 return 0; 194 } 195 196 void spi_release_bus(struct spi_slave *slave) 197 { 198 } 199 200 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 201 void *din, unsigned long flags) 202 { 203 struct sh_qspi_slave *ss = to_sh_qspi(slave); 204 u32 nbyte; 205 int ret = 0; 206 u8 dtdata = 0, drdata; 207 u8 *tdata = &dtdata, *rdata = &drdata; 208 u32 *spbmul0 = &ss->regs->spbmul0; 209 210 if (dout == NULL && din == NULL) { 211 if (flags & SPI_XFER_END) 212 spi_cs_deactivate(slave); 213 return 0; 214 } 215 216 if (bitlen % 8) { 217 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); 218 return 1; 219 } 220 221 nbyte = bitlen / 8; 222 223 if (flags & SPI_XFER_BEGIN) { 224 spi_cs_activate(slave); 225 226 /* Set 1048576 byte */ 227 writel(0x100000, spbmul0); 228 } 229 230 if (flags & SPI_XFER_END) 231 writel(nbyte, spbmul0); 232 233 if (dout != NULL) 234 tdata = (u8 *)dout; 235 236 if (din != NULL) 237 rdata = din; 238 239 while (nbyte > 0) { 240 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF, 241 true, 1000, true); 242 if (ret) 243 return ret; 244 245 writeb(*tdata, (u8 *)(&ss->regs->spdr)); 246 247 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF, 248 true, 1000, true); 249 if (ret) 250 return ret; 251 252 *rdata = readb((u8 *)(&ss->regs->spdr)); 253 254 if (dout != NULL) 255 tdata++; 256 if (din != NULL) 257 rdata++; 258 259 nbyte--; 260 } 261 262 if (flags & SPI_XFER_END) 263 spi_cs_deactivate(slave); 264 265 return ret; 266 } 267