1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <pci.h> 15 #include <pci_ids.h> 16 #include <asm/io.h> 17 18 #include "ich.h" 19 20 #define SPI_OPCODE_WREN 0x06 21 #define SPI_OPCODE_FAST_READ 0x0b 22 23 #ifdef DEBUG_TRACE 24 #define debug_trace(fmt, args...) debug(fmt, ##args) 25 #else 26 #define debug_trace(x, args...) 27 #endif 28 29 struct ich_spi_platdata { 30 pci_dev_t dev; /* PCI device number */ 31 int ich_version; /* Controller version, 7 or 9 */ 32 bool use_sbase; /* Use SBASE instead of RCB */ 33 }; 34 35 struct ich_spi_priv { 36 int ichspi_lock; 37 int locked; 38 int opmenu; 39 int menubytes; 40 void *base; /* Base of register set */ 41 int preop; 42 int optype; 43 int addr; 44 int data; 45 unsigned databytes; 46 int status; 47 int control; 48 int bbar; 49 int bcr; 50 uint32_t *pr; /* only for ich9 */ 51 int speed; /* pointer to speed control */ 52 ulong max_speed; /* Maximum bus speed in MHz */ 53 ulong cur_speed; /* Current bus speed */ 54 struct spi_trans trans; /* current transaction in progress */ 55 }; 56 57 static u8 ich_readb(struct ich_spi_priv *priv, int reg) 58 { 59 u8 value = readb(priv->base + reg); 60 61 debug_trace("read %2.2x from %4.4x\n", value, reg); 62 63 return value; 64 } 65 66 static u16 ich_readw(struct ich_spi_priv *priv, int reg) 67 { 68 u16 value = readw(priv->base + reg); 69 70 debug_trace("read %4.4x from %4.4x\n", value, reg); 71 72 return value; 73 } 74 75 static u32 ich_readl(struct ich_spi_priv *priv, int reg) 76 { 77 u32 value = readl(priv->base + reg); 78 79 debug_trace("read %8.8x from %4.4x\n", value, reg); 80 81 return value; 82 } 83 84 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) 85 { 86 writeb(value, priv->base + reg); 87 debug_trace("wrote %2.2x to %4.4x\n", value, reg); 88 } 89 90 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) 91 { 92 writew(value, priv->base + reg); 93 debug_trace("wrote %4.4x to %4.4x\n", value, reg); 94 } 95 96 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) 97 { 98 writel(value, priv->base + reg); 99 debug_trace("wrote %8.8x to %4.4x\n", value, reg); 100 } 101 102 static void write_reg(struct ich_spi_priv *priv, const void *value, 103 int dest_reg, uint32_t size) 104 { 105 memcpy_toio(priv->base + dest_reg, value, size); 106 } 107 108 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, 109 uint32_t size) 110 { 111 memcpy_fromio(value, priv->base + src_reg, size); 112 } 113 114 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) 115 { 116 const uint32_t bbar_mask = 0x00ffff00; 117 uint32_t ichspi_bbar; 118 119 minaddr &= bbar_mask; 120 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; 121 ichspi_bbar |= minaddr; 122 ich_writel(ctlr, ichspi_bbar, ctlr->bbar); 123 } 124 125 /* 126 * Check if this device ID matches one of supported Intel PCH devices. 127 * 128 * Return the ICH version if there is a match, or zero otherwise. 129 */ 130 static int get_ich_version(uint16_t device_id) 131 { 132 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || 133 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || 134 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) 135 return 7; 136 137 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 138 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 139 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 140 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || 141 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || 142 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC || 143 device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC) 144 return 9; 145 146 return 0; 147 } 148 149 /* @return 1 if the SPI flash supports the 33MHz speed */ 150 static int ich9_can_do_33mhz(pci_dev_t dev) 151 { 152 u32 fdod, speed; 153 154 /* Observe SPI Descriptor Component Section 0 */ 155 pci_write_config_dword(dev, 0xb0, 0x1000); 156 157 /* Extract the Write/Erase SPI Frequency from descriptor */ 158 pci_read_config_dword(dev, 0xb4, &fdod); 159 160 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 161 speed = (fdod >> 21) & 7; 162 163 return speed == 1; 164 } 165 166 static int ich_find_spi_controller(struct ich_spi_platdata *ich) 167 { 168 int last_bus = pci_last_busno(); 169 int bus; 170 171 if (last_bus == -1) { 172 debug("No PCI busses?\n"); 173 return -ENODEV; 174 } 175 176 for (bus = 0; bus <= last_bus; bus++) { 177 uint16_t vendor_id, device_id; 178 uint32_t ids; 179 pci_dev_t dev; 180 181 dev = PCI_BDF(bus, 31, 0); 182 pci_read_config_dword(dev, 0, &ids); 183 vendor_id = ids; 184 device_id = ids >> 16; 185 186 if (vendor_id == PCI_VENDOR_ID_INTEL) { 187 ich->dev = dev; 188 ich->ich_version = get_ich_version(device_id); 189 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) 190 ich->use_sbase = true; 191 return ich->ich_version == 0 ? -ENODEV : 0; 192 } 193 } 194 195 debug("ICH SPI: No ICH found.\n"); 196 return -ENODEV; 197 } 198 199 static int ich_init_controller(struct ich_spi_platdata *plat, 200 struct ich_spi_priv *ctlr) 201 { 202 uint8_t *rcrb; /* Root Complex Register Block */ 203 uint32_t rcba; /* Root Complex Base Address */ 204 uint32_t sbase_addr; 205 uint8_t *sbase; 206 207 pci_read_config_dword(plat->dev, 0xf0, &rcba); 208 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 209 rcrb = (uint8_t *)(rcba & 0xffffc000); 210 211 /* SBASE is similar */ 212 pci_read_config_dword(plat->dev, 0x54, &sbase_addr); 213 sbase = (uint8_t *)(sbase_addr & 0xfffffe00); 214 215 if (plat->ich_version == 7) { 216 struct ich7_spi_regs *ich7_spi; 217 218 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 219 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; 220 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); 221 ctlr->menubytes = sizeof(ich7_spi->opmenu); 222 ctlr->optype = offsetof(struct ich7_spi_regs, optype); 223 ctlr->addr = offsetof(struct ich7_spi_regs, spia); 224 ctlr->data = offsetof(struct ich7_spi_regs, spid); 225 ctlr->databytes = sizeof(ich7_spi->spid); 226 ctlr->status = offsetof(struct ich7_spi_regs, spis); 227 ctlr->control = offsetof(struct ich7_spi_regs, spic); 228 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); 229 ctlr->preop = offsetof(struct ich7_spi_regs, preop); 230 ctlr->base = ich7_spi; 231 } else if (plat->ich_version == 9) { 232 struct ich9_spi_regs *ich9_spi; 233 234 if (plat->use_sbase) 235 ich9_spi = (struct ich9_spi_regs *)sbase; 236 else 237 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 238 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 239 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); 240 ctlr->menubytes = sizeof(ich9_spi->opmenu); 241 ctlr->optype = offsetof(struct ich9_spi_regs, optype); 242 ctlr->addr = offsetof(struct ich9_spi_regs, faddr); 243 ctlr->data = offsetof(struct ich9_spi_regs, fdata); 244 ctlr->databytes = sizeof(ich9_spi->fdata); 245 ctlr->status = offsetof(struct ich9_spi_regs, ssfs); 246 ctlr->control = offsetof(struct ich9_spi_regs, ssfc); 247 ctlr->speed = ctlr->control + 2; 248 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); 249 ctlr->preop = offsetof(struct ich9_spi_regs, preop); 250 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); 251 ctlr->pr = &ich9_spi->pr[0]; 252 ctlr->base = ich9_spi; 253 } else { 254 debug("ICH SPI: Unrecognised ICH version %d\n", 255 plat->ich_version); 256 return -EINVAL; 257 } 258 259 /* Work out the maximum speed we can support */ 260 ctlr->max_speed = 20000000; 261 if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev)) 262 ctlr->max_speed = 33000000; 263 debug("ICH SPI: Version %d detected at %p, speed %ld\n", 264 plat->ich_version, ctlr->base, ctlr->max_speed); 265 266 ich_set_bbar(ctlr, 0); 267 268 return 0; 269 } 270 271 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 272 { 273 trans->out += bytes; 274 trans->bytesout -= bytes; 275 } 276 277 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 278 { 279 trans->in += bytes; 280 trans->bytesin -= bytes; 281 } 282 283 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 284 { 285 trans->type = 0xFF; 286 287 /* Try to guess spi type from read/write sizes. */ 288 if (trans->bytesin == 0) { 289 if (trans->bytesout + data_bytes > 4) 290 /* 291 * If bytesin = 0 and bytesout > 4, we presume this is 292 * a write data operation, which is accompanied by an 293 * address. 294 */ 295 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 296 else 297 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 298 return; 299 } 300 301 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 302 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 303 return; 304 } 305 306 if (trans->bytesout == 4) /* and bytesin is > 0 */ 307 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 308 309 /* Fast read command is called with 5 bytes instead of 4 */ 310 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 311 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 312 --trans->bytesout; 313 } 314 } 315 316 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) 317 { 318 uint16_t optypes; 319 uint8_t opmenu[ctlr->menubytes]; 320 321 trans->opcode = trans->out[0]; 322 spi_use_out(trans, 1); 323 if (!ctlr->ichspi_lock) { 324 /* The lock is off, so just use index 0. */ 325 ich_writeb(ctlr, trans->opcode, ctlr->opmenu); 326 optypes = ich_readw(ctlr, ctlr->optype); 327 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 328 ich_writew(ctlr, optypes, ctlr->optype); 329 return 0; 330 } else { 331 /* The lock is on. See if what we need is on the menu. */ 332 uint8_t optype; 333 uint16_t opcode_index; 334 335 /* Write Enable is handled as atomic prefix */ 336 if (trans->opcode == SPI_OPCODE_WREN) 337 return 0; 338 339 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); 340 for (opcode_index = 0; opcode_index < ctlr->menubytes; 341 opcode_index++) { 342 if (opmenu[opcode_index] == trans->opcode) 343 break; 344 } 345 346 if (opcode_index == ctlr->menubytes) { 347 printf("ICH SPI: Opcode %x not found\n", 348 trans->opcode); 349 return -EINVAL; 350 } 351 352 optypes = ich_readw(ctlr, ctlr->optype); 353 optype = (optypes >> (opcode_index * 2)) & 0x3; 354 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 355 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 356 trans->bytesout >= 3) { 357 /* We guessed wrong earlier. Fix it up. */ 358 trans->type = optype; 359 } 360 if (optype != trans->type) { 361 printf("ICH SPI: Transaction doesn't fit type %d\n", 362 optype); 363 return -ENOSPC; 364 } 365 return opcode_index; 366 } 367 } 368 369 static int spi_setup_offset(struct spi_trans *trans) 370 { 371 /* Separate the SPI address and data. */ 372 switch (trans->type) { 373 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 374 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 375 return 0; 376 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 377 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 378 trans->offset = ((uint32_t)trans->out[0] << 16) | 379 ((uint32_t)trans->out[1] << 8) | 380 ((uint32_t)trans->out[2] << 0); 381 spi_use_out(trans, 3); 382 return 1; 383 default: 384 printf("Unrecognized SPI transaction type %#x\n", trans->type); 385 return -EPROTO; 386 } 387 } 388 389 /* 390 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 391 * below is true) or 0. In case the wait was for the bit(s) to set - write 392 * those bits back, which would cause resetting them. 393 * 394 * Return the last read status value on success or -1 on failure. 395 */ 396 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, 397 int wait_til_set) 398 { 399 int timeout = 600000; /* This will result in 6s */ 400 u16 status = 0; 401 402 while (timeout--) { 403 status = ich_readw(ctlr, ctlr->status); 404 if (wait_til_set ^ ((status & bitmask) == 0)) { 405 if (wait_til_set) { 406 ich_writew(ctlr, status & bitmask, 407 ctlr->status); 408 } 409 return status; 410 } 411 udelay(10); 412 } 413 414 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 415 status, bitmask); 416 return -ETIMEDOUT; 417 } 418 419 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, 420 const void *dout, void *din, unsigned long flags) 421 { 422 struct udevice *bus = dev_get_parent(dev); 423 struct ich_spi_platdata *plat = dev_get_platdata(bus); 424 struct ich_spi_priv *ctlr = dev_get_priv(bus); 425 uint16_t control; 426 int16_t opcode_index; 427 int with_address; 428 int status; 429 int bytes = bitlen / 8; 430 struct spi_trans *trans = &ctlr->trans; 431 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 432 int using_cmd = 0; 433 int ret; 434 435 /* We don't support writing partial bytes */ 436 if (bitlen % 8) { 437 debug("ICH SPI: Accessing partial bytes not supported\n"); 438 return -EPROTONOSUPPORT; 439 } 440 441 /* An empty end transaction can be ignored */ 442 if (type == SPI_XFER_END && !dout && !din) 443 return 0; 444 445 if (type & SPI_XFER_BEGIN) 446 memset(trans, '\0', sizeof(*trans)); 447 448 /* Dp we need to come back later to finish it? */ 449 if (dout && type == SPI_XFER_BEGIN) { 450 if (bytes > ICH_MAX_CMD_LEN) { 451 debug("ICH SPI: Command length limit exceeded\n"); 452 return -ENOSPC; 453 } 454 memcpy(trans->cmd, dout, bytes); 455 trans->cmd_len = bytes; 456 debug_trace("ICH SPI: Saved %d bytes\n", bytes); 457 return 0; 458 } 459 460 /* 461 * We process a 'middle' spi_xfer() call, which has no 462 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 463 * an end. We therefore repeat the command. This is because ICH 464 * seems to have no support for this, or because interest (in digging 465 * out the details and creating a special case in the code) is low. 466 */ 467 if (trans->cmd_len) { 468 trans->out = trans->cmd; 469 trans->bytesout = trans->cmd_len; 470 using_cmd = 1; 471 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); 472 } else { 473 trans->out = dout; 474 trans->bytesout = dout ? bytes : 0; 475 } 476 477 trans->in = din; 478 trans->bytesin = din ? bytes : 0; 479 480 /* There has to always at least be an opcode. */ 481 if (!trans->bytesout) { 482 debug("ICH SPI: No opcode for transfer\n"); 483 return -EPROTO; 484 } 485 486 ret = ich_status_poll(ctlr, SPIS_SCIP, 0); 487 if (ret < 0) 488 return ret; 489 490 if (plat->ich_version == 7) 491 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 492 else 493 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 494 495 spi_setup_type(trans, using_cmd ? bytes : 0); 496 opcode_index = spi_setup_opcode(ctlr, trans); 497 if (opcode_index < 0) 498 return -EINVAL; 499 with_address = spi_setup_offset(trans); 500 if (with_address < 0) 501 return -EINVAL; 502 503 if (trans->opcode == SPI_OPCODE_WREN) { 504 /* 505 * Treat Write Enable as Atomic Pre-Op if possible 506 * in order to prevent the Management Engine from 507 * issuing a transaction between WREN and DATA. 508 */ 509 if (!ctlr->ichspi_lock) 510 ich_writew(ctlr, trans->opcode, ctlr->preop); 511 return 0; 512 } 513 514 if (ctlr->speed && ctlr->max_speed >= 33000000) { 515 int byte; 516 517 byte = ich_readb(ctlr, ctlr->speed); 518 if (ctlr->cur_speed >= 33000000) 519 byte |= SSFC_SCF_33MHZ; 520 else 521 byte &= ~SSFC_SCF_33MHZ; 522 ich_writeb(ctlr, byte, ctlr->speed); 523 } 524 525 /* See if we have used up the command data */ 526 if (using_cmd && dout && bytes) { 527 trans->out = dout; 528 trans->bytesout = bytes; 529 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); 530 } 531 532 /* Preset control fields */ 533 control = ich_readw(ctlr, ctlr->control); 534 control &= ~SSFC_RESERVED; 535 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 536 537 /* Issue atomic preop cycle if needed */ 538 if (ich_readw(ctlr, ctlr->preop)) 539 control |= SPIC_ACS; 540 541 if (!trans->bytesout && !trans->bytesin) { 542 /* SPI addresses are 24 bit only */ 543 if (with_address) { 544 ich_writel(ctlr, trans->offset & 0x00FFFFFF, 545 ctlr->addr); 546 } 547 /* 548 * This is a 'no data' command (like Write Enable), its 549 * bitesout size was 1, decremented to zero while executing 550 * spi_setup_opcode() above. Tell the chip to send the 551 * command. 552 */ 553 ich_writew(ctlr, control, ctlr->control); 554 555 /* wait for the result */ 556 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 557 if (status < 0) 558 return status; 559 560 if (status & SPIS_FCERR) { 561 debug("ICH SPI: Command transaction error\n"); 562 return -EIO; 563 } 564 565 return 0; 566 } 567 568 /* 569 * Check if this is a write command atempting to transfer more bytes 570 * than the controller can handle. Iterations for writes are not 571 * supported here because each SPI write command needs to be preceded 572 * and followed by other SPI commands, and this sequence is controlled 573 * by the SPI chip driver. 574 */ 575 if (trans->bytesout > ctlr->databytes) { 576 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 577 return -EPROTO; 578 } 579 580 /* 581 * Read or write up to databytes bytes at a time until everything has 582 * been sent. 583 */ 584 while (trans->bytesout || trans->bytesin) { 585 uint32_t data_length; 586 587 /* SPI addresses are 24 bit only */ 588 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); 589 590 if (trans->bytesout) 591 data_length = min(trans->bytesout, ctlr->databytes); 592 else 593 data_length = min(trans->bytesin, ctlr->databytes); 594 595 /* Program data into FDATA0 to N */ 596 if (trans->bytesout) { 597 write_reg(ctlr, trans->out, ctlr->data, data_length); 598 spi_use_out(trans, data_length); 599 if (with_address) 600 trans->offset += data_length; 601 } 602 603 /* Add proper control fields' values */ 604 control &= ~((ctlr->databytes - 1) << 8); 605 control |= SPIC_DS; 606 control |= (data_length - 1) << 8; 607 608 /* write it */ 609 ich_writew(ctlr, control, ctlr->control); 610 611 /* Wait for Cycle Done Status or Flash Cycle Error. */ 612 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 613 if (status < 0) 614 return status; 615 616 if (status & SPIS_FCERR) { 617 debug("ICH SPI: Data transaction error %x\n", status); 618 return -EIO; 619 } 620 621 if (trans->bytesin) { 622 read_reg(ctlr, ctlr->data, trans->in, data_length); 623 spi_use_in(trans, data_length); 624 if (with_address) 625 trans->offset += data_length; 626 } 627 } 628 629 /* Clear atomic preop now that xfer is done */ 630 ich_writew(ctlr, 0, ctlr->preop); 631 632 return 0; 633 } 634 635 /* 636 * This uses the SPI controller from the Intel Cougar Point and Panther Point 637 * PCH to write-protect portions of the SPI flash until reboot. The changes 638 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 639 * done elsewhere. 640 */ 641 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, 642 uint32_t length, int hint) 643 { 644 struct udevice *bus = dev->parent; 645 struct ich_spi_priv *ctlr = dev_get_priv(bus); 646 uint32_t tmplong; 647 uint32_t upper_limit; 648 649 if (!ctlr->pr) { 650 printf("%s: operation not supported on this chipset\n", 651 __func__); 652 return -ENOSYS; 653 } 654 655 if (length == 0 || 656 lower_limit > (0xFFFFFFFFUL - length) + 1 || 657 hint < 0 || hint > 4) { 658 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 659 lower_limit, length, hint); 660 return -EPERM; 661 } 662 663 upper_limit = lower_limit + length - 1; 664 665 /* 666 * Determine bits to write, as follows: 667 * 31 Write-protection enable (includes erase operation) 668 * 30:29 reserved 669 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 670 * 15 Read-protection enable 671 * 14:13 reserved 672 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 673 */ 674 tmplong = 0x80000000 | 675 ((upper_limit & 0x01fff000) << 4) | 676 ((lower_limit & 0x01fff000) >> 12); 677 678 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 679 &ctlr->pr[hint]); 680 ctlr->pr[hint] = tmplong; 681 682 return 0; 683 } 684 685 static int ich_spi_probe(struct udevice *bus) 686 { 687 struct ich_spi_platdata *plat = dev_get_platdata(bus); 688 struct ich_spi_priv *priv = dev_get_priv(bus); 689 uint8_t bios_cntl; 690 int ret; 691 692 ret = ich_init_controller(plat, priv); 693 if (ret) 694 return ret; 695 /* 696 * Disable the BIOS write protect so write commands are allowed. On 697 * v9, deassert SMM BIOS Write Protect Disable. 698 */ 699 if (plat->use_sbase) { 700 bios_cntl = ich_readb(priv, priv->bcr); 701 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ 702 bios_cntl |= 1; /* Write Protect Disable (WPD) */ 703 ich_writeb(priv, bios_cntl, priv->bcr); 704 } else { 705 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); 706 if (plat->ich_version == 9) 707 bios_cntl &= ~BIT(5); 708 pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); 709 } 710 711 priv->cur_speed = priv->max_speed; 712 713 return 0; 714 } 715 716 static int ich_spi_ofdata_to_platdata(struct udevice *bus) 717 { 718 struct ich_spi_platdata *plat = dev_get_platdata(bus); 719 int ret; 720 721 ret = ich_find_spi_controller(plat); 722 if (ret) 723 return ret; 724 725 return 0; 726 } 727 728 static int ich_spi_set_speed(struct udevice *bus, uint speed) 729 { 730 struct ich_spi_priv *priv = dev_get_priv(bus); 731 732 priv->cur_speed = speed; 733 734 return 0; 735 } 736 737 static int ich_spi_set_mode(struct udevice *bus, uint mode) 738 { 739 debug("%s: mode=%d\n", __func__, mode); 740 741 return 0; 742 } 743 744 static int ich_spi_child_pre_probe(struct udevice *dev) 745 { 746 struct udevice *bus = dev_get_parent(dev); 747 struct ich_spi_platdata *plat = dev_get_platdata(bus); 748 struct ich_spi_priv *priv = dev_get_priv(bus); 749 struct spi_slave *slave = dev_get_parent_priv(dev); 750 751 /* 752 * Yes this controller can only write a small number of bytes at 753 * once! The limit is typically 64 bytes. 754 */ 755 slave->max_write_size = priv->databytes; 756 /* 757 * ICH 7 SPI controller only supports array read command 758 * and byte program command for SST flash 759 */ 760 if (plat->ich_version == 7) { 761 slave->mode_rx = SPI_RX_SLOW; 762 slave->mode = SPI_TX_BYTE; 763 } 764 765 return 0; 766 } 767 768 static const struct dm_spi_ops ich_spi_ops = { 769 .xfer = ich_spi_xfer, 770 .set_speed = ich_spi_set_speed, 771 .set_mode = ich_spi_set_mode, 772 /* 773 * cs_info is not needed, since we require all chip selects to be 774 * in the device tree explicitly 775 */ 776 }; 777 778 static const struct udevice_id ich_spi_ids[] = { 779 { .compatible = "intel,ich-spi" }, 780 { } 781 }; 782 783 U_BOOT_DRIVER(ich_spi) = { 784 .name = "ich_spi", 785 .id = UCLASS_SPI, 786 .of_match = ich_spi_ids, 787 .ops = &ich_spi_ops, 788 .ofdata_to_platdata = ich_spi_ofdata_to_platdata, 789 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), 790 .priv_auto_alloc_size = sizeof(struct ich_spi_priv), 791 .child_pre_probe = ich_spi_child_pre_probe, 792 .probe = ich_spi_probe, 793 }; 794