1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 20 #define BIT_WRITEABLE_SHIFT 16 21 22 struct rockchip_combphy_priv; 23 24 struct combphy_reg { 25 u16 offset; 26 u16 bitend; 27 u16 bitstart; 28 u16 disable; 29 u16 enable; 30 }; 31 32 struct rockchip_combphy_grfcfg { 33 struct combphy_reg pcie_mode_set; 34 struct combphy_reg usb_mode_set; 35 struct combphy_reg sgmii_mode_set; 36 struct combphy_reg qsgmii_mode_set; 37 struct combphy_reg pipe_rxterm_set; 38 struct combphy_reg pipe_txelec_set; 39 struct combphy_reg pipe_txcomp_set; 40 struct combphy_reg pipe_clk_25m; 41 struct combphy_reg pipe_clk_100m; 42 struct combphy_reg pipe_phymode_sel; 43 struct combphy_reg pipe_rate_sel; 44 struct combphy_reg pipe_rxterm_sel; 45 struct combphy_reg pipe_txelec_sel; 46 struct combphy_reg pipe_txcomp_sel; 47 struct combphy_reg pipe_clk_ext; 48 struct combphy_reg pipe_sel_usb; 49 struct combphy_reg pipe_sel_qsgmii; 50 struct combphy_reg pipe_phy_status; 51 struct combphy_reg con0_for_pcie; 52 struct combphy_reg con1_for_pcie; 53 struct combphy_reg con2_for_pcie; 54 struct combphy_reg con3_for_pcie; 55 struct combphy_reg con0_for_sata; 56 struct combphy_reg con1_for_sata; 57 struct combphy_reg con2_for_sata; 58 struct combphy_reg con3_for_sata; 59 struct combphy_reg pipe_con0_for_sata; 60 struct combphy_reg pipe_con1_for_sata; 61 struct combphy_reg pipe_sgmii_mac_sel; 62 struct combphy_reg pipe_xpcs_phy_ready; 63 struct combphy_reg u3otg0_port_en; 64 struct combphy_reg u3otg1_port_en; 65 }; 66 67 struct rockchip_combphy_cfg { 68 const struct rockchip_combphy_grfcfg *grfcfg; 69 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 70 }; 71 72 struct rockchip_combphy_priv { 73 u32 mode; 74 void __iomem *mmio; 75 struct udevice *dev; 76 struct regmap *pipe_grf; 77 struct regmap *phy_grf; 78 struct phy *phy; 79 struct reset_ctl phy_rst; 80 struct clk ref_clk; 81 const struct rockchip_combphy_cfg *cfg; 82 }; 83 84 static int param_write(struct regmap *base, 85 const struct combphy_reg *reg, bool en) 86 { 87 u32 val, mask, tmp; 88 89 tmp = en ? reg->enable : reg->disable; 90 mask = GENMASK(reg->bitend, reg->bitstart); 91 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 92 93 return regmap_write(base, reg->offset, val); 94 } 95 96 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 97 { 98 int ret = 0; 99 100 if (priv->cfg->combphy_cfg) { 101 ret = priv->cfg->combphy_cfg(priv); 102 if (ret) { 103 dev_err(priv->dev, "failed to init phy for pcie\n"); 104 return ret; 105 } 106 } 107 108 return ret; 109 } 110 111 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 112 { 113 int ret = 0; 114 115 if (priv->cfg->combphy_cfg) { 116 ret = priv->cfg->combphy_cfg(priv); 117 if (ret) { 118 dev_err(priv->dev, "failed to init phy for usb3\n"); 119 return ret; 120 } 121 } 122 123 return ret; 124 } 125 126 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 127 { 128 int ret = 0; 129 130 if (priv->cfg->combphy_cfg) { 131 ret = priv->cfg->combphy_cfg(priv); 132 if (ret) { 133 dev_err(priv->dev, "failed to init phy for sata\n"); 134 return ret; 135 } 136 } 137 138 return ret; 139 } 140 141 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 142 { 143 int ret = 0; 144 145 if (priv->cfg->combphy_cfg) { 146 ret = priv->cfg->combphy_cfg(priv); 147 if (ret) { 148 dev_err(priv->dev, "failed to init phy for sgmii\n"); 149 return ret; 150 } 151 } 152 153 return ret; 154 } 155 156 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 157 { 158 switch (priv->mode) { 159 case PHY_TYPE_PCIE: 160 rockchip_combphy_pcie_init(priv); 161 break; 162 case PHY_TYPE_USB3: 163 rockchip_combphy_usb3_init(priv); 164 break; 165 case PHY_TYPE_SATA: 166 rockchip_combphy_sata_init(priv); 167 break; 168 case PHY_TYPE_SGMII: 169 case PHY_TYPE_QSGMII: 170 return rockchip_combphy_sgmii_init(priv); 171 default: 172 dev_err(priv->dev, "incompatible PHY type\n"); 173 return -EINVAL; 174 } 175 176 return 0; 177 } 178 179 static int rockchip_combphy_init(struct phy *phy) 180 { 181 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 182 int ret; 183 184 ret = clk_enable(&priv->ref_clk); 185 if (ret < 0 && ret != -ENOSYS) 186 return ret; 187 188 ret = rockchip_combphy_set_mode(priv); 189 if (ret) 190 goto err_clk; 191 192 reset_deassert(&priv->phy_rst); 193 194 return 0; 195 196 err_clk: 197 clk_disable(&priv->ref_clk); 198 199 return ret; 200 } 201 202 static int rockchip_combphy_exit(struct phy *phy) 203 { 204 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 205 206 clk_disable(&priv->ref_clk); 207 reset_assert(&priv->phy_rst); 208 209 return 0; 210 } 211 212 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 213 { 214 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 215 216 if (args->args_count != 1) { 217 pr_err("invalid number of arguments\n"); 218 return -EINVAL; 219 } 220 221 priv->mode = args->args[0]; 222 223 return 0; 224 } 225 226 static const struct phy_ops rochchip_combphy_ops = { 227 .init = rockchip_combphy_init, 228 .exit = rockchip_combphy_exit, 229 .of_xlate = rockchip_combphy_xlate, 230 }; 231 232 static int rockchip_combphy_parse_dt(struct udevice *dev, 233 struct rockchip_combphy_priv *priv) 234 { 235 struct udevice *syscon; 236 int ret; 237 238 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 239 if (ret) { 240 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 241 return ret; 242 } 243 priv->pipe_grf = syscon_get_regmap(syscon); 244 245 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 246 if (ret) { 247 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 248 return ret; 249 } 250 priv->phy_grf = syscon_get_regmap(syscon); 251 252 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 253 if (ret) { 254 dev_err(dev, "failed to find ref clock\n"); 255 return PTR_ERR(&priv->ref_clk); 256 } 257 258 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 259 if (ret) { 260 dev_err(dev, "no phy reset control specified\n"); 261 return ret; 262 } 263 264 return 0; 265 } 266 267 static int rockchip_combphy_probe(struct udevice *udev) 268 { 269 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 270 const struct rockchip_combphy_cfg *phy_cfg; 271 int ret; 272 273 priv->mmio = (void __iomem *)dev_read_addr(udev); 274 if (IS_ERR(priv->mmio)) 275 return PTR_ERR(priv->mmio); 276 277 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 278 if (!phy_cfg) { 279 dev_err(udev, "No OF match data provided\n"); 280 return -EINVAL; 281 } 282 283 priv->dev = udev; 284 priv->mode = PHY_TYPE_SATA; 285 priv->cfg = phy_cfg; 286 287 ret = rockchip_combphy_parse_dt(udev, priv); 288 if (ret) 289 return ret; 290 291 ret = rockchip_combphy_set_mode(priv); 292 293 return ret; 294 } 295 296 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 297 { 298 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 299 u32 val; 300 301 switch (priv->mode) { 302 case PHY_TYPE_PCIE: 303 /* Set SSC downward spread spectrum */ 304 val = readl(priv->mmio + (0x1f << 2)); 305 val &= ~GENMASK(5, 4); 306 val |= 0x01 << 4; 307 writel(val, priv->mmio + 0x7c); 308 309 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 310 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 311 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 312 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 313 break; 314 case PHY_TYPE_USB3: 315 /* Set SSC downward spread spectrum */ 316 val = readl(priv->mmio + (0x1f << 2)); 317 val &= ~GENMASK(5, 4); 318 val |= 0x01 << 4; 319 writel(val, priv->mmio + 0x7c); 320 321 /* Enable adaptive CTLE for USB3.0 Rx */ 322 val = readl(priv->mmio + (0x0e << 2)); 323 val &= ~GENMASK(0, 0); 324 val |= 0x01; 325 writel(val, priv->mmio + (0x0e << 2)); 326 327 /* Set PLL KVCO fine tuning signals */ 328 val = readl(priv->mmio + (0x20 << 2)); 329 val &= ~(0x7 << 2); 330 val |= 0x2 << 2; 331 writel(val, priv->mmio + (0x20 << 2)); 332 333 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 334 writel(0x4, priv->mmio + (0xb << 2)); 335 336 /* Set PLL input clock divider 1/2 */ 337 val = readl(priv->mmio + (0x5 << 2)); 338 val &= ~(0x3 << 6); 339 val |= 0x1 << 6; 340 writel(val, priv->mmio + (0x5 << 2)); 341 342 /* Set PLL loop divider */ 343 writel(0x32, priv->mmio + (0x11 << 2)); 344 345 /* Set PLL KVCO to min and set PLL charge pump current to max */ 346 writel(0xf0, priv->mmio + (0xa << 2)); 347 348 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 349 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 350 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 351 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 352 break; 353 case PHY_TYPE_SATA: 354 writel(0x41, priv->mmio + 0x38); 355 writel(0x8F, priv->mmio + 0x18); 356 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 357 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 358 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 359 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 360 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 361 break; 362 case PHY_TYPE_SGMII: 363 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 364 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 365 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 366 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 367 break; 368 case PHY_TYPE_QSGMII: 369 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 370 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 371 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 372 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 373 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 374 break; 375 default: 376 pr_err("%s, phy-type %d\n", __func__, priv->mode); 377 return -EINVAL; 378 } 379 380 /* The default ref clock is 25Mhz */ 381 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 382 383 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 384 val = readl(priv->mmio + (0x7 << 2)); 385 val |= BIT(4); 386 writel(val, priv->mmio + (0x7 << 2)); 387 } 388 389 return 0; 390 } 391 392 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 393 /* pipe-phy-grf */ 394 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 395 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 396 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 397 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 398 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 399 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 400 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 401 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 402 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 403 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 404 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 405 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 406 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 407 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 408 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 409 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 410 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 411 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 412 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 413 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 414 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 415 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 416 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 417 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 418 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 419 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 420 /* pipe-grf */ 421 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 422 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 423 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 424 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 425 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 426 }; 427 428 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 429 .grfcfg = &rk3568_combphy_grfcfgs, 430 .combphy_cfg = rk3568_combphy_cfg, 431 }; 432 433 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 434 { 435 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 436 437 switch (priv->mode) { 438 case PHY_TYPE_PCIE: 439 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 440 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 441 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 442 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 443 break; 444 case PHY_TYPE_USB3: 445 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 446 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 447 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 448 break; 449 case PHY_TYPE_SATA: 450 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 451 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 452 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 453 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 454 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 455 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 456 break; 457 case PHY_TYPE_SGMII: 458 case PHY_TYPE_QSGMII: 459 default: 460 dev_err(priv->dev, "incompatible PHY type\n"); 461 return -EINVAL; 462 } 463 464 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 465 466 return 0; 467 } 468 469 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 470 /* pipe-phy-grf */ 471 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 472 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 473 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 474 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 475 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 476 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 477 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 478 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 479 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 480 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 481 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 482 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 483 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 484 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 485 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 486 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 487 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 488 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 489 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 490 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 491 /* pipe-grf */ 492 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 493 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 494 }; 495 496 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 497 .grfcfg = &rk3588_combphy_grfcfgs, 498 .combphy_cfg = rk3588_combphy_cfg, 499 }; 500 501 static const struct udevice_id rockchip_combphy_ids[] = { 502 { 503 .compatible = "rockchip,rk3568-naneng-combphy", 504 .data = (ulong)&rk3568_combphy_cfgs 505 }, 506 { 507 .compatible = "rockchip,rk3588-naneng-combphy", 508 .data = (ulong)&rk3588_combphy_cfgs 509 }, 510 { } 511 }; 512 513 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 514 .name = "naneng-combphy", 515 .id = UCLASS_PHY, 516 .of_match = rockchip_combphy_ids, 517 .ops = &rochchip_combphy_ops, 518 .probe = rockchip_combphy_probe, 519 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 520 }; 521