net: tsec: Fix Marvell 88E1121R phy init

This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 8

net: tsec: Fix Marvell 88E1121R phy init

This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

Merge git://git.denx.de/u-boot into x1

Conflicts:

drivers/usb/usb_ohci.c

Merge 'next' branch

Conflicts:

board/freescale/mpc8536ds/mpc8536ds.c
include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Merge branch 'master' of git://git.denx.de/u-boot-net

enable 10/100M at VSC8601 at tsec driver

Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.

Signed-off-by: Andre S

enable 10/100M at VSC8601 at tsec driver

Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Support for multiple SGMII/TBI interfaces for TSEC ethernet

Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/wri

Support for multiple SGMII/TBI interfaces for TSEC ethernet

Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>

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Merge branch 'master' of ssh://10.10.0.7/home/wd/git/u-boot/master

Merge branch 'master' of git://git.denx.de/u-boot-net

Add SGMII support to the tsec

Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@

Add SGMII support to the tsec

Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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Pass in tsec_info struct through tsec_initialize

The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works

Pass in tsec_info struct through tsec_initialize

The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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tsec: Move tsec.h to include/

This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadd

tsec: Move tsec.h to include/

This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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PHY: Add support for the M88E1121R Marvell chip.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gm

PHY: Add support for the M88E1121R Marvell chip.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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Merge branch 'master' of git://www.denx.de/git/u-boot

Merge branch 'master' of git://www.denx.de/git/u-boot-net

net: Conditional COBJS inclusion of network drivers

Replace COBJS-y with appropriate driver config names.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <bigg

net: Conditional COBJS inclusion of network drivers

Replace COBJS-y with appropriate driver config names.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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Add Marvell 88E1118 support for TSEC

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Merge branch 'master' of /home/wd/git/u-boot/master/

drivers/net/tsec.c: Fix typo.

Signed-off-by: Wolfgang Denk <wd@denx.de>

TSEC: add config options for VSC8601 RGMII PHY

The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore

TSEC: add config options for VSC8601 RGMII PHY

The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
--

drivers/net/tsec.c | 6 ++++++
drivers/net/tsec.h | 3 +++
2 files changed, 9 insertions(+), 0 deletions(-)

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Merge branch 'master' of git://www.denx.de/git/u-boot-net

Add Vitesse 8601 support to TSEC driver

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by: Tor Krill <tor@excito.com>

Add Vitesse 8601 support to TSEC driver

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

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