1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 #define MAXCONTROLLERS (8) 36 37 static int relocated = 0; 38 39 static struct tsec_private *privlist[MAXCONTROLLERS]; 40 static int num_tsecs = 0; 41 42 #ifdef __GNUC__ 43 static RTXBD rtx __attribute__ ((aligned(8))); 44 #else 45 #error "rtx must be 64-bit aligned" 46 #endif 47 48 static int tsec_send(struct eth_device *dev, 49 volatile void *packet, int length); 50 static int tsec_recv(struct eth_device *dev); 51 static int tsec_init(struct eth_device *dev, bd_t * bd); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 struct phy_info *get_phy_info(struct eth_device *dev); 59 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 static void relocate_cmds(void); 62 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 63 && !defined(BITBANGMII) 64 static int tsec_miiphy_write(char *devname, unsigned char addr, 65 unsigned char reg, unsigned short value); 66 static int tsec_miiphy_read(char *devname, unsigned char addr, 67 unsigned char reg, unsigned short *value); 68 #endif 69 #ifdef CONFIG_MCAST_TFTP 70 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 71 #endif 72 73 /* Default initializations for TSEC controllers. */ 74 75 static struct tsec_info_struct tsec_info[] = { 76 #ifdef CONFIG_TSEC1 77 STD_TSEC_INFO(1), /* TSEC1 */ 78 #endif 79 #ifdef CONFIG_TSEC2 80 STD_TSEC_INFO(2), /* TSEC2 */ 81 #endif 82 #ifdef CONFIG_MPC85XX_FEC 83 { 84 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 85 .miiregs = (tsec_t *)(TSEC_BASE_ADDR), 86 .devname = CONFIG_MPC85XX_FEC_NAME, 87 .phyaddr = FEC_PHY_ADDR, 88 .flags = FEC_FLAGS 89 }, /* FEC */ 90 #endif 91 #ifdef CONFIG_TSEC3 92 STD_TSEC_INFO(3), /* TSEC3 */ 93 #endif 94 #ifdef CONFIG_TSEC4 95 STD_TSEC_INFO(4), /* TSEC4 */ 96 #endif 97 }; 98 99 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 100 { 101 int i; 102 103 for (i = 0; i < num; i++) 104 tsec_initialize(bis, &tsecs[i]); 105 106 return 0; 107 } 108 109 int tsec_standard_init(bd_t *bis) 110 { 111 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 112 } 113 114 /* Initialize device structure. Returns success if PHY 115 * initialization succeeded (i.e. if it recognizes the PHY) 116 */ 117 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 118 { 119 struct eth_device *dev; 120 int i; 121 struct tsec_private *priv; 122 123 dev = (struct eth_device *)malloc(sizeof *dev); 124 125 if (NULL == dev) 126 return 0; 127 128 memset(dev, 0, sizeof *dev); 129 130 priv = (struct tsec_private *)malloc(sizeof(*priv)); 131 132 if (NULL == priv) 133 return 0; 134 135 privlist[num_tsecs++] = priv; 136 priv->regs = tsec_info->regs; 137 priv->phyregs = tsec_info->miiregs; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 162 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 164 && !defined(BITBANGMII) 165 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 166 #endif 167 168 /* Try to initialize PHY here, and return */ 169 return init_phy(dev); 170 } 171 172 /* Initializes data structures and registers for the controller, 173 * and brings the interface up. Returns the link status, meaning 174 * that it returns success if the link is up, failure otherwise. 175 * This allows u-boot to find the first active controller. 176 */ 177 int tsec_init(struct eth_device *dev, bd_t * bd) 178 { 179 uint tempval; 180 char tmpbuf[MAC_ADDR_LEN]; 181 int i; 182 struct tsec_private *priv = (struct tsec_private *)dev->priv; 183 volatile tsec_t *regs = priv->regs; 184 185 /* Make sure the controller is stopped */ 186 tsec_halt(dev); 187 188 /* Init MACCFG2. Defaults to GMII */ 189 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 190 191 /* Init ECNTRL */ 192 regs->ecntrl = ECNTRL_INIT_SETTINGS; 193 194 /* Copy the station address into the address registers. 195 * Backwards, because little endian MACS are dumb */ 196 for (i = 0; i < MAC_ADDR_LEN; i++) { 197 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 198 } 199 regs->macstnaddr1 = *((uint *) (tmpbuf)); 200 201 tempval = *((uint *) (tmpbuf + 4)); 202 203 regs->macstnaddr2 = tempval; 204 205 /* reset the indices to zero */ 206 rxIdx = 0; 207 txIdx = 0; 208 209 /* Clear out (for the most part) the other registers */ 210 init_registers(regs); 211 212 /* Ready the device for tx/rx */ 213 startup_tsec(dev); 214 215 /* If there's no link, fail */ 216 return (priv->link ? 0 : -1); 217 } 218 219 /* Write value to the device's PHY through the registers 220 * specified in priv, modifying the register specified in regnum. 221 * It will wait for the write to be done (or for a timeout to 222 * expire) before exiting 223 */ 224 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 225 { 226 volatile tsec_t *regbase = priv->phyregs; 227 int timeout = 1000000; 228 229 regbase->miimadd = (phyid << 8) | regnum; 230 regbase->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 /* #define to provide old write_phy_reg functionality without duplicating code */ 238 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 239 240 /* Reads register regnum on the device's PHY through the 241 * registers specified in priv. It lowers and raises the read 242 * command, and waits for the data to become valid (miimind 243 * notvalid bit cleared), and the bus to cease activity (miimind 244 * busy bit cleared), and then returns the value 245 */ 246 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 247 { 248 uint value; 249 volatile tsec_t *regbase = priv->phyregs; 250 251 /* Put the address of the phy, and the register 252 * number into MIIMADD */ 253 regbase->miimadd = (phyid << 8) | regnum; 254 255 /* Clear the command register, and wait */ 256 regbase->miimcom = 0; 257 asm("sync"); 258 259 /* Initiate a read command, and wait */ 260 regbase->miimcom = MIIM_READ_COMMAND; 261 asm("sync"); 262 263 /* Wait for the the indication that the read is done */ 264 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 265 266 /* Grab the value read from the PHY */ 267 value = regbase->miimstat; 268 269 return value; 270 } 271 272 /* #define to provide old read_phy_reg functionality without duplicating code */ 273 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 274 275 /* Discover which PHY is attached to the device, and configure it 276 * properly. If the PHY is not recognized, then return 0 277 * (failure). Otherwise, return 1 278 */ 279 static int init_phy(struct eth_device *dev) 280 { 281 struct tsec_private *priv = (struct tsec_private *)dev->priv; 282 struct phy_info *curphy; 283 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 284 285 /* Assign a Physical address to the TBI */ 286 regs->tbipa = CFG_TBIPA_VALUE; 287 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 288 regs->tbipa = CFG_TBIPA_VALUE; 289 asm("sync"); 290 291 /* Reset MII (due to new addresses) */ 292 priv->phyregs->miimcfg = MIIMCFG_RESET; 293 asm("sync"); 294 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 295 asm("sync"); 296 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 297 298 if (0 == relocated) 299 relocate_cmds(); 300 301 /* Get the cmd structure corresponding to the attached 302 * PHY */ 303 curphy = get_phy_info(dev); 304 305 if (curphy == NULL) { 306 priv->phyinfo = NULL; 307 printf("%s: No PHY found\n", dev->name); 308 309 return 0; 310 } 311 312 priv->phyinfo = curphy; 313 314 phy_run_commands(priv, priv->phyinfo->config); 315 316 return 1; 317 } 318 319 /* 320 * Returns which value to write to the control register. 321 * For 10/100, the value is slightly different 322 */ 323 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 324 { 325 if (priv->flags & TSEC_GIGABIT) 326 return MIIM_CONTROL_INIT; 327 else 328 return MIIM_CR_INIT; 329 } 330 331 /* Parse the status register for link, and then do 332 * auto-negotiation 333 */ 334 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 335 { 336 /* 337 * Wait if the link is up, and autonegotiation is in progress 338 * (ie - we're capable and it's not done) 339 */ 340 mii_reg = read_phy_reg(priv, MIIM_STATUS); 341 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 342 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 343 int i = 0; 344 345 puts("Waiting for PHY auto negotiation to complete"); 346 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 347 /* 348 * Timeout reached ? 349 */ 350 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 351 puts(" TIMEOUT !\n"); 352 priv->link = 0; 353 return 0; 354 } 355 356 if ((i++ % 1000) == 0) { 357 putc('.'); 358 } 359 udelay(1000); /* 1 ms */ 360 mii_reg = read_phy_reg(priv, MIIM_STATUS); 361 } 362 puts(" done\n"); 363 priv->link = 1; 364 udelay(500000); /* another 500 ms (results in faster booting) */ 365 } else { 366 if (mii_reg & MIIM_STATUS_LINK) 367 priv->link = 1; 368 else 369 priv->link = 0; 370 } 371 372 return 0; 373 } 374 375 /* Generic function which updates the speed and duplex. If 376 * autonegotiation is enabled, it uses the AND of the link 377 * partner's advertised capabilities and our advertised 378 * capabilities. If autonegotiation is disabled, we use the 379 * appropriate bits in the control register. 380 * 381 * Stolen from Linux's mii.c and phy_device.c 382 */ 383 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 384 { 385 /* We're using autonegotiation */ 386 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 387 uint lpa = 0; 388 uint gblpa = 0; 389 390 /* Check for gigabit capability */ 391 if (mii_reg & PHY_BMSR_EXT) { 392 /* We want a list of states supported by 393 * both PHYs in the link 394 */ 395 gblpa = read_phy_reg(priv, PHY_1000BTSR); 396 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 397 } 398 399 /* Set the baseline so we only have to set them 400 * if they're different 401 */ 402 priv->speed = 10; 403 priv->duplexity = 0; 404 405 /* Check the gigabit fields */ 406 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 407 priv->speed = 1000; 408 409 if (gblpa & PHY_1000BTSR_1000FD) 410 priv->duplexity = 1; 411 412 /* We're done! */ 413 return 0; 414 } 415 416 lpa = read_phy_reg(priv, PHY_ANAR); 417 lpa &= read_phy_reg(priv, PHY_ANLPAR); 418 419 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 420 priv->speed = 100; 421 422 if (lpa & PHY_ANLPAR_TXFD) 423 priv->duplexity = 1; 424 425 } else if (lpa & PHY_ANLPAR_10FD) 426 priv->duplexity = 1; 427 } else { 428 uint bmcr = read_phy_reg(priv, PHY_BMCR); 429 430 priv->speed = 10; 431 priv->duplexity = 0; 432 433 if (bmcr & PHY_BMCR_DPLX) 434 priv->duplexity = 1; 435 436 if (bmcr & PHY_BMCR_1000_MBPS) 437 priv->speed = 1000; 438 else if (bmcr & PHY_BMCR_100_MBPS) 439 priv->speed = 100; 440 } 441 442 return 0; 443 } 444 445 /* 446 * Parse the BCM54xx status register for speed and duplex information. 447 * The linux sungem_phy has this information, but in a table format. 448 */ 449 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 450 { 451 452 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 453 454 case 1: 455 printf("Enet starting in 10BT/HD\n"); 456 priv->duplexity = 0; 457 priv->speed = 10; 458 break; 459 460 case 2: 461 printf("Enet starting in 10BT/FD\n"); 462 priv->duplexity = 1; 463 priv->speed = 10; 464 break; 465 466 case 3: 467 printf("Enet starting in 100BT/HD\n"); 468 priv->duplexity = 0; 469 priv->speed = 100; 470 break; 471 472 case 5: 473 printf("Enet starting in 100BT/FD\n"); 474 priv->duplexity = 1; 475 priv->speed = 100; 476 break; 477 478 case 6: 479 printf("Enet starting in 1000BT/HD\n"); 480 priv->duplexity = 0; 481 priv->speed = 1000; 482 break; 483 484 case 7: 485 printf("Enet starting in 1000BT/FD\n"); 486 priv->duplexity = 1; 487 priv->speed = 1000; 488 break; 489 490 default: 491 printf("Auto-neg error, defaulting to 10BT/HD\n"); 492 priv->duplexity = 0; 493 priv->speed = 10; 494 break; 495 } 496 497 return 0; 498 499 } 500 /* Parse the 88E1011's status register for speed and duplex 501 * information 502 */ 503 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 504 { 505 uint speed; 506 507 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 508 509 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 510 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 511 int i = 0; 512 513 puts("Waiting for PHY realtime link"); 514 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 515 /* Timeout reached ? */ 516 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 517 puts(" TIMEOUT !\n"); 518 priv->link = 0; 519 break; 520 } 521 522 if ((i++ % 1000) == 0) { 523 putc('.'); 524 } 525 udelay(1000); /* 1 ms */ 526 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 527 } 528 puts(" done\n"); 529 udelay(500000); /* another 500 ms (results in faster booting) */ 530 } else { 531 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 532 priv->link = 1; 533 else 534 priv->link = 0; 535 } 536 537 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 538 priv->duplexity = 1; 539 else 540 priv->duplexity = 0; 541 542 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 543 544 switch (speed) { 545 case MIIM_88E1011_PHYSTAT_GBIT: 546 priv->speed = 1000; 547 break; 548 case MIIM_88E1011_PHYSTAT_100: 549 priv->speed = 100; 550 break; 551 default: 552 priv->speed = 10; 553 } 554 555 return 0; 556 } 557 558 /* Parse the RTL8211B's status register for speed and duplex 559 * information 560 */ 561 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 562 { 563 uint speed; 564 565 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 566 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 567 int i = 0; 568 569 /* in case of timeout ->link is cleared */ 570 priv->link = 1; 571 puts("Waiting for PHY realtime link"); 572 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 573 /* Timeout reached ? */ 574 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 575 puts(" TIMEOUT !\n"); 576 priv->link = 0; 577 break; 578 } 579 580 if ((i++ % 1000) == 0) { 581 putc('.'); 582 } 583 udelay(1000); /* 1 ms */ 584 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 585 } 586 puts(" done\n"); 587 udelay(500000); /* another 500 ms (results in faster booting) */ 588 } else { 589 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 590 priv->link = 1; 591 else 592 priv->link = 0; 593 } 594 595 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 596 priv->duplexity = 1; 597 else 598 priv->duplexity = 0; 599 600 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 601 602 switch (speed) { 603 case MIIM_RTL8211B_PHYSTAT_GBIT: 604 priv->speed = 1000; 605 break; 606 case MIIM_RTL8211B_PHYSTAT_100: 607 priv->speed = 100; 608 break; 609 default: 610 priv->speed = 10; 611 } 612 613 return 0; 614 } 615 616 /* Parse the cis8201's status register for speed and duplex 617 * information 618 */ 619 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 620 { 621 uint speed; 622 623 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 624 priv->duplexity = 1; 625 else 626 priv->duplexity = 0; 627 628 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 629 switch (speed) { 630 case MIIM_CIS8201_AUXCONSTAT_GBIT: 631 priv->speed = 1000; 632 break; 633 case MIIM_CIS8201_AUXCONSTAT_100: 634 priv->speed = 100; 635 break; 636 default: 637 priv->speed = 10; 638 break; 639 } 640 641 return 0; 642 } 643 644 /* Parse the vsc8244's status register for speed and duplex 645 * information 646 */ 647 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 648 { 649 uint speed; 650 651 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 652 priv->duplexity = 1; 653 else 654 priv->duplexity = 0; 655 656 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 657 switch (speed) { 658 case MIIM_VSC8244_AUXCONSTAT_GBIT: 659 priv->speed = 1000; 660 break; 661 case MIIM_VSC8244_AUXCONSTAT_100: 662 priv->speed = 100; 663 break; 664 default: 665 priv->speed = 10; 666 break; 667 } 668 669 return 0; 670 } 671 672 /* Parse the DM9161's status register for speed and duplex 673 * information 674 */ 675 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 676 { 677 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 678 priv->speed = 100; 679 else 680 priv->speed = 10; 681 682 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 683 priv->duplexity = 1; 684 else 685 priv->duplexity = 0; 686 687 return 0; 688 } 689 690 /* 691 * Hack to write all 4 PHYs with the LED values 692 */ 693 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 694 { 695 uint phyid; 696 volatile tsec_t *regbase = priv->phyregs; 697 int timeout = 1000000; 698 699 for (phyid = 0; phyid < 4; phyid++) { 700 regbase->miimadd = (phyid << 8) | mii_reg; 701 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 702 asm("sync"); 703 704 timeout = 1000000; 705 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 706 } 707 708 return MIIM_CIS8204_SLEDCON_INIT; 709 } 710 711 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 712 { 713 if (priv->flags & TSEC_REDUCED) 714 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 715 else 716 return MIIM_CIS8204_EPHYCON_INIT; 717 } 718 719 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 720 { 721 uint mii_data = read_phy_reg(priv, mii_reg); 722 723 if (priv->flags & TSEC_REDUCED) 724 mii_data = (mii_data & 0xfff0) | 0x000b; 725 return mii_data; 726 } 727 728 /* Initialized required registers to appropriate values, zeroing 729 * those we don't care about (unless zero is bad, in which case, 730 * choose a more appropriate value) 731 */ 732 static void init_registers(volatile tsec_t * regs) 733 { 734 /* Clear IEVENT */ 735 regs->ievent = IEVENT_INIT_CLEAR; 736 737 regs->imask = IMASK_INIT_CLEAR; 738 739 regs->hash.iaddr0 = 0; 740 regs->hash.iaddr1 = 0; 741 regs->hash.iaddr2 = 0; 742 regs->hash.iaddr3 = 0; 743 regs->hash.iaddr4 = 0; 744 regs->hash.iaddr5 = 0; 745 regs->hash.iaddr6 = 0; 746 regs->hash.iaddr7 = 0; 747 748 regs->hash.gaddr0 = 0; 749 regs->hash.gaddr1 = 0; 750 regs->hash.gaddr2 = 0; 751 regs->hash.gaddr3 = 0; 752 regs->hash.gaddr4 = 0; 753 regs->hash.gaddr5 = 0; 754 regs->hash.gaddr6 = 0; 755 regs->hash.gaddr7 = 0; 756 757 regs->rctrl = 0x00000000; 758 759 /* Init RMON mib registers */ 760 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 761 762 regs->rmon.cam1 = 0xffffffff; 763 regs->rmon.cam2 = 0xffffffff; 764 765 regs->mrblr = MRBLR_INIT_SETTINGS; 766 767 regs->minflr = MINFLR_INIT_SETTINGS; 768 769 regs->attr = ATTR_INIT_SETTINGS; 770 regs->attreli = ATTRELI_INIT_SETTINGS; 771 772 } 773 774 /* Configure maccfg2 based on negotiated speed and duplex 775 * reported by PHY handling code 776 */ 777 static void adjust_link(struct eth_device *dev) 778 { 779 struct tsec_private *priv = (struct tsec_private *)dev->priv; 780 volatile tsec_t *regs = priv->regs; 781 782 if (priv->link) { 783 if (priv->duplexity != 0) 784 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 785 else 786 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 787 788 switch (priv->speed) { 789 case 1000: 790 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 791 | MACCFG2_GMII); 792 break; 793 case 100: 794 case 10: 795 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 796 | MACCFG2_MII); 797 798 /* Set R100 bit in all modes although 799 * it is only used in RGMII mode 800 */ 801 if (priv->speed == 100) 802 regs->ecntrl |= ECNTRL_R100; 803 else 804 regs->ecntrl &= ~(ECNTRL_R100); 805 break; 806 default: 807 printf("%s: Speed was bad\n", dev->name); 808 break; 809 } 810 811 printf("Speed: %d, %s duplex\n", priv->speed, 812 (priv->duplexity) ? "full" : "half"); 813 814 } else { 815 printf("%s: No link.\n", dev->name); 816 } 817 } 818 819 /* Set up the buffers and their descriptors, and bring up the 820 * interface 821 */ 822 static void startup_tsec(struct eth_device *dev) 823 { 824 int i; 825 struct tsec_private *priv = (struct tsec_private *)dev->priv; 826 volatile tsec_t *regs = priv->regs; 827 828 /* Point to the buffer descriptors */ 829 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 830 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 831 832 /* Initialize the Rx Buffer descriptors */ 833 for (i = 0; i < PKTBUFSRX; i++) { 834 rtx.rxbd[i].status = RXBD_EMPTY; 835 rtx.rxbd[i].length = 0; 836 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 837 } 838 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 839 840 /* Initialize the TX Buffer Descriptors */ 841 for (i = 0; i < TX_BUF_CNT; i++) { 842 rtx.txbd[i].status = 0; 843 rtx.txbd[i].length = 0; 844 rtx.txbd[i].bufPtr = 0; 845 } 846 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 847 848 /* Start up the PHY */ 849 if(priv->phyinfo) 850 phy_run_commands(priv, priv->phyinfo->startup); 851 852 adjust_link(dev); 853 854 /* Enable Transmit and Receive */ 855 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 856 857 /* Tell the DMA it is clear to go */ 858 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 859 regs->tstat = TSTAT_CLEAR_THALT; 860 regs->rstat = RSTAT_CLEAR_RHALT; 861 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 862 } 863 864 /* This returns the status bits of the device. The return value 865 * is never checked, and this is what the 8260 driver did, so we 866 * do the same. Presumably, this would be zero if there were no 867 * errors 868 */ 869 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 870 { 871 int i; 872 int result = 0; 873 struct tsec_private *priv = (struct tsec_private *)dev->priv; 874 volatile tsec_t *regs = priv->regs; 875 876 /* Find an empty buffer descriptor */ 877 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 878 if (i >= TOUT_LOOP) { 879 debug("%s: tsec: tx buffers full\n", dev->name); 880 return result; 881 } 882 } 883 884 rtx.txbd[txIdx].bufPtr = (uint) packet; 885 rtx.txbd[txIdx].length = length; 886 rtx.txbd[txIdx].status |= 887 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 888 889 /* Tell the DMA to go */ 890 regs->tstat = TSTAT_CLEAR_THALT; 891 892 /* Wait for buffer to be transmitted */ 893 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 894 if (i >= TOUT_LOOP) { 895 debug("%s: tsec: tx error\n", dev->name); 896 return result; 897 } 898 } 899 900 txIdx = (txIdx + 1) % TX_BUF_CNT; 901 result = rtx.txbd[txIdx].status & TXBD_STATS; 902 903 return result; 904 } 905 906 static int tsec_recv(struct eth_device *dev) 907 { 908 int length; 909 struct tsec_private *priv = (struct tsec_private *)dev->priv; 910 volatile tsec_t *regs = priv->regs; 911 912 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 913 914 length = rtx.rxbd[rxIdx].length; 915 916 /* Send the packet up if there were no errors */ 917 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 918 NetReceive(NetRxPackets[rxIdx], length - 4); 919 } else { 920 printf("Got error %x\n", 921 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 922 } 923 924 rtx.rxbd[rxIdx].length = 0; 925 926 /* Set the wrap bit if this is the last element in the list */ 927 rtx.rxbd[rxIdx].status = 928 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 929 930 rxIdx = (rxIdx + 1) % PKTBUFSRX; 931 } 932 933 if (regs->ievent & IEVENT_BSY) { 934 regs->ievent = IEVENT_BSY; 935 regs->rstat = RSTAT_CLEAR_RHALT; 936 } 937 938 return -1; 939 940 } 941 942 /* Stop the interface */ 943 static void tsec_halt(struct eth_device *dev) 944 { 945 struct tsec_private *priv = (struct tsec_private *)dev->priv; 946 volatile tsec_t *regs = priv->regs; 947 948 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 949 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 950 951 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 952 953 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 954 955 /* Shut down the PHY, as needed */ 956 if(priv->phyinfo) 957 phy_run_commands(priv, priv->phyinfo->shutdown); 958 } 959 960 struct phy_info phy_info_M88E1149S = { 961 0x1410ca, 962 "Marvell 88E1149S", 963 4, 964 (struct phy_cmd[]){ /* config */ 965 /* Reset and configure the PHY */ 966 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 967 {0x1d, 0x1f, NULL}, 968 {0x1e, 0x200c, NULL}, 969 {0x1d, 0x5, NULL}, 970 {0x1e, 0x0, NULL}, 971 {0x1e, 0x100, NULL}, 972 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 973 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 974 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 975 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 976 {miim_end,} 977 }, 978 (struct phy_cmd[]){ /* startup */ 979 /* Status is read once to clear old link state */ 980 {MIIM_STATUS, miim_read, NULL}, 981 /* Auto-negotiate */ 982 {MIIM_STATUS, miim_read, &mii_parse_sr}, 983 /* Read the status */ 984 {MIIM_88E1011_PHY_STATUS, miim_read, 985 &mii_parse_88E1011_psr}, 986 {miim_end,} 987 }, 988 (struct phy_cmd[]){ /* shutdown */ 989 {miim_end,} 990 }, 991 }; 992 993 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 994 struct phy_info phy_info_BCM5461S = { 995 0x02060c1, /* 5461 ID */ 996 "Broadcom BCM5461S", 997 0, /* not clear to me what minor revisions we can shift away */ 998 (struct phy_cmd[]) { /* config */ 999 /* Reset and configure the PHY */ 1000 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1001 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1002 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1003 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1004 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1005 {miim_end,} 1006 }, 1007 (struct phy_cmd[]) { /* startup */ 1008 /* Status is read once to clear old link state */ 1009 {MIIM_STATUS, miim_read, NULL}, 1010 /* Auto-negotiate */ 1011 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1012 /* Read the status */ 1013 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1014 {miim_end,} 1015 }, 1016 (struct phy_cmd[]) { /* shutdown */ 1017 {miim_end,} 1018 }, 1019 }; 1020 1021 struct phy_info phy_info_BCM5464S = { 1022 0x02060b1, /* 5464 ID */ 1023 "Broadcom BCM5464S", 1024 0, /* not clear to me what minor revisions we can shift away */ 1025 (struct phy_cmd[]) { /* config */ 1026 /* Reset and configure the PHY */ 1027 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1028 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1029 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1030 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1031 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1032 {miim_end,} 1033 }, 1034 (struct phy_cmd[]) { /* startup */ 1035 /* Status is read once to clear old link state */ 1036 {MIIM_STATUS, miim_read, NULL}, 1037 /* Auto-negotiate */ 1038 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1039 /* Read the status */ 1040 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1041 {miim_end,} 1042 }, 1043 (struct phy_cmd[]) { /* shutdown */ 1044 {miim_end,} 1045 }, 1046 }; 1047 1048 struct phy_info phy_info_M88E1011S = { 1049 0x01410c6, 1050 "Marvell 88E1011S", 1051 4, 1052 (struct phy_cmd[]){ /* config */ 1053 /* Reset and configure the PHY */ 1054 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1055 {0x1d, 0x1f, NULL}, 1056 {0x1e, 0x200c, NULL}, 1057 {0x1d, 0x5, NULL}, 1058 {0x1e, 0x0, NULL}, 1059 {0x1e, 0x100, NULL}, 1060 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1061 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1062 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1063 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1064 {miim_end,} 1065 }, 1066 (struct phy_cmd[]){ /* startup */ 1067 /* Status is read once to clear old link state */ 1068 {MIIM_STATUS, miim_read, NULL}, 1069 /* Auto-negotiate */ 1070 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1071 /* Read the status */ 1072 {MIIM_88E1011_PHY_STATUS, miim_read, 1073 &mii_parse_88E1011_psr}, 1074 {miim_end,} 1075 }, 1076 (struct phy_cmd[]){ /* shutdown */ 1077 {miim_end,} 1078 }, 1079 }; 1080 1081 struct phy_info phy_info_M88E1111S = { 1082 0x01410cc, 1083 "Marvell 88E1111S", 1084 4, 1085 (struct phy_cmd[]){ /* config */ 1086 /* Reset and configure the PHY */ 1087 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1088 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1089 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1090 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1091 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1092 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1093 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1094 {miim_end,} 1095 }, 1096 (struct phy_cmd[]){ /* startup */ 1097 /* Status is read once to clear old link state */ 1098 {MIIM_STATUS, miim_read, NULL}, 1099 /* Auto-negotiate */ 1100 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1101 /* Read the status */ 1102 {MIIM_88E1011_PHY_STATUS, miim_read, 1103 &mii_parse_88E1011_psr}, 1104 {miim_end,} 1105 }, 1106 (struct phy_cmd[]){ /* shutdown */ 1107 {miim_end,} 1108 }, 1109 }; 1110 1111 struct phy_info phy_info_M88E1118 = { 1112 0x01410e1, 1113 "Marvell 88E1118", 1114 4, 1115 (struct phy_cmd[]){ /* config */ 1116 /* Reset and configure the PHY */ 1117 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1118 {0x16, 0x0002, NULL}, /* Change Page Number */ 1119 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1120 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1121 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1122 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1123 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1124 {miim_end,} 1125 }, 1126 (struct phy_cmd[]){ /* startup */ 1127 {0x16, 0x0000, NULL}, /* Change Page Number */ 1128 /* Status is read once to clear old link state */ 1129 {MIIM_STATUS, miim_read, NULL}, 1130 /* Auto-negotiate */ 1131 /* Read the status */ 1132 {MIIM_88E1011_PHY_STATUS, miim_read, 1133 &mii_parse_88E1011_psr}, 1134 {miim_end,} 1135 }, 1136 (struct phy_cmd[]){ /* shutdown */ 1137 {miim_end,} 1138 }, 1139 }; 1140 1141 /* 1142 * Since to access LED register we need do switch the page, we 1143 * do LED configuring in the miim_read-like function as follows 1144 */ 1145 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1146 { 1147 uint pg; 1148 1149 /* Switch the page to access the led register */ 1150 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1151 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1152 1153 /* Configure leds */ 1154 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1155 MIIM_88E1121_PHY_LED_DEF); 1156 1157 /* Restore the page pointer */ 1158 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1159 return 0; 1160 } 1161 1162 struct phy_info phy_info_M88E1121R = { 1163 0x01410cb, 1164 "Marvell 88E1121R", 1165 4, 1166 (struct phy_cmd[]){ /* config */ 1167 /* Reset and configure the PHY */ 1168 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1169 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1170 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1171 /* Configure leds */ 1172 {MIIM_88E1121_PHY_LED_CTRL, miim_read, 1173 &mii_88E1121_set_led}, 1174 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1175 {miim_end,} 1176 }, 1177 (struct phy_cmd[]){ /* startup */ 1178 /* Status is read once to clear old link state */ 1179 {MIIM_STATUS, miim_read, NULL}, 1180 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1181 {MIIM_STATUS, miim_read, &mii_parse_link}, 1182 {miim_end,} 1183 }, 1184 (struct phy_cmd[]){ /* shutdown */ 1185 {miim_end,} 1186 }, 1187 }; 1188 1189 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1190 { 1191 uint mii_data = read_phy_reg(priv, mii_reg); 1192 1193 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1194 if (priv->flags & TSEC_REDUCED) 1195 return mii_data | 1196 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1197 else 1198 return mii_data; 1199 } 1200 1201 static struct phy_info phy_info_M88E1145 = { 1202 0x01410cd, 1203 "Marvell 88E1145", 1204 4, 1205 (struct phy_cmd[]){ /* config */ 1206 /* Reset the PHY */ 1207 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1208 1209 /* Errata E0, E1 */ 1210 {29, 0x001b, NULL}, 1211 {30, 0x418f, NULL}, 1212 {29, 0x0016, NULL}, 1213 {30, 0xa2da, NULL}, 1214 1215 /* Configure the PHY */ 1216 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1217 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1218 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1219 NULL}, 1220 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1221 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1222 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1223 {miim_end,} 1224 }, 1225 (struct phy_cmd[]){ /* startup */ 1226 /* Status is read once to clear old link state */ 1227 {MIIM_STATUS, miim_read, NULL}, 1228 /* Auto-negotiate */ 1229 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1230 {MIIM_88E1111_PHY_LED_CONTROL, 1231 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1232 /* Read the Status */ 1233 {MIIM_88E1011_PHY_STATUS, miim_read, 1234 &mii_parse_88E1011_psr}, 1235 {miim_end,} 1236 }, 1237 (struct phy_cmd[]){ /* shutdown */ 1238 {miim_end,} 1239 }, 1240 }; 1241 1242 struct phy_info phy_info_cis8204 = { 1243 0x3f11, 1244 "Cicada Cis8204", 1245 6, 1246 (struct phy_cmd[]){ /* config */ 1247 /* Override PHY config settings */ 1248 {MIIM_CIS8201_AUX_CONSTAT, 1249 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1250 /* Configure some basic stuff */ 1251 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1252 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1253 &mii_cis8204_fixled}, 1254 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1255 &mii_cis8204_setmode}, 1256 {miim_end,} 1257 }, 1258 (struct phy_cmd[]){ /* startup */ 1259 /* Read the Status (2x to make sure link is right) */ 1260 {MIIM_STATUS, miim_read, NULL}, 1261 /* Auto-negotiate */ 1262 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1263 /* Read the status */ 1264 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1265 &mii_parse_cis8201}, 1266 {miim_end,} 1267 }, 1268 (struct phy_cmd[]){ /* shutdown */ 1269 {miim_end,} 1270 }, 1271 }; 1272 1273 /* Cicada 8201 */ 1274 struct phy_info phy_info_cis8201 = { 1275 0xfc41, 1276 "CIS8201", 1277 4, 1278 (struct phy_cmd[]){ /* config */ 1279 /* Override PHY config settings */ 1280 {MIIM_CIS8201_AUX_CONSTAT, 1281 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1282 /* Set up the interface mode */ 1283 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1284 NULL}, 1285 /* Configure some basic stuff */ 1286 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1287 {miim_end,} 1288 }, 1289 (struct phy_cmd[]){ /* startup */ 1290 /* Read the Status (2x to make sure link is right) */ 1291 {MIIM_STATUS, miim_read, NULL}, 1292 /* Auto-negotiate */ 1293 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1294 /* Read the status */ 1295 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1296 &mii_parse_cis8201}, 1297 {miim_end,} 1298 }, 1299 (struct phy_cmd[]){ /* shutdown */ 1300 {miim_end,} 1301 }, 1302 }; 1303 struct phy_info phy_info_VSC8244 = { 1304 0x3f1b, 1305 "Vitesse VSC8244", 1306 6, 1307 (struct phy_cmd[]){ /* config */ 1308 /* Override PHY config settings */ 1309 /* Configure some basic stuff */ 1310 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1311 {miim_end,} 1312 }, 1313 (struct phy_cmd[]){ /* startup */ 1314 /* Read the Status (2x to make sure link is right) */ 1315 {MIIM_STATUS, miim_read, NULL}, 1316 /* Auto-negotiate */ 1317 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1318 /* Read the status */ 1319 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1320 &mii_parse_vsc8244}, 1321 {miim_end,} 1322 }, 1323 (struct phy_cmd[]){ /* shutdown */ 1324 {miim_end,} 1325 }, 1326 }; 1327 1328 struct phy_info phy_info_VSC8601 = { 1329 0x00007042, 1330 "Vitesse VSC8601", 1331 4, 1332 (struct phy_cmd[]){ /* config */ 1333 /* Override PHY config settings */ 1334 /* Configure some basic stuff */ 1335 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1336 #ifdef CFG_VSC8601_SKEWFIX 1337 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1338 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) 1339 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1340 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) 1341 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1342 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1343 #endif 1344 #endif 1345 {miim_end,} 1346 }, 1347 (struct phy_cmd[]){ /* startup */ 1348 /* Read the Status (2x to make sure link is right) */ 1349 {MIIM_STATUS, miim_read, NULL}, 1350 /* Auto-negotiate */ 1351 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1352 /* Read the status */ 1353 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1354 &mii_parse_vsc8244}, 1355 {miim_end,} 1356 }, 1357 (struct phy_cmd[]){ /* shutdown */ 1358 {miim_end,} 1359 }, 1360 }; 1361 1362 1363 struct phy_info phy_info_dm9161 = { 1364 0x0181b88, 1365 "Davicom DM9161E", 1366 4, 1367 (struct phy_cmd[]){ /* config */ 1368 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1369 /* Do not bypass the scrambler/descrambler */ 1370 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1371 /* Clear 10BTCSR to default */ 1372 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1373 NULL}, 1374 /* Configure some basic stuff */ 1375 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1376 /* Restart Auto Negotiation */ 1377 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1378 {miim_end,} 1379 }, 1380 (struct phy_cmd[]){ /* startup */ 1381 /* Status is read once to clear old link state */ 1382 {MIIM_STATUS, miim_read, NULL}, 1383 /* Auto-negotiate */ 1384 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1385 /* Read the status */ 1386 {MIIM_DM9161_SCSR, miim_read, 1387 &mii_parse_dm9161_scsr}, 1388 {miim_end,} 1389 }, 1390 (struct phy_cmd[]){ /* shutdown */ 1391 {miim_end,} 1392 }, 1393 }; 1394 /* a generic flavor. */ 1395 struct phy_info phy_info_generic = { 1396 0, 1397 "Unknown/Generic PHY", 1398 32, 1399 (struct phy_cmd[]) { /* config */ 1400 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1401 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1402 {miim_end,} 1403 }, 1404 (struct phy_cmd[]) { /* startup */ 1405 {PHY_BMSR, miim_read, NULL}, 1406 {PHY_BMSR, miim_read, &mii_parse_sr}, 1407 {PHY_BMSR, miim_read, &mii_parse_link}, 1408 {miim_end,} 1409 }, 1410 (struct phy_cmd[]) { /* shutdown */ 1411 {miim_end,} 1412 } 1413 }; 1414 1415 1416 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1417 { 1418 unsigned int speed; 1419 if (priv->link) { 1420 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1421 1422 switch (speed) { 1423 case MIIM_LXT971_SR2_10HDX: 1424 priv->speed = 10; 1425 priv->duplexity = 0; 1426 break; 1427 case MIIM_LXT971_SR2_10FDX: 1428 priv->speed = 10; 1429 priv->duplexity = 1; 1430 break; 1431 case MIIM_LXT971_SR2_100HDX: 1432 priv->speed = 100; 1433 priv->duplexity = 0; 1434 break; 1435 default: 1436 priv->speed = 100; 1437 priv->duplexity = 1; 1438 } 1439 } else { 1440 priv->speed = 0; 1441 priv->duplexity = 0; 1442 } 1443 1444 return 0; 1445 } 1446 1447 static struct phy_info phy_info_lxt971 = { 1448 0x0001378e, 1449 "LXT971", 1450 4, 1451 (struct phy_cmd[]){ /* config */ 1452 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1453 {miim_end,} 1454 }, 1455 (struct phy_cmd[]){ /* startup - enable interrupts */ 1456 /* { 0x12, 0x00f2, NULL }, */ 1457 {MIIM_STATUS, miim_read, NULL}, 1458 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1459 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1460 {miim_end,} 1461 }, 1462 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1463 {miim_end,} 1464 }, 1465 }; 1466 1467 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1468 * information 1469 */ 1470 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1471 { 1472 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1473 1474 case MIIM_DP83865_SPD_1000: 1475 priv->speed = 1000; 1476 break; 1477 1478 case MIIM_DP83865_SPD_100: 1479 priv->speed = 100; 1480 break; 1481 1482 default: 1483 priv->speed = 10; 1484 break; 1485 1486 } 1487 1488 if (mii_reg & MIIM_DP83865_DPX_FULL) 1489 priv->duplexity = 1; 1490 else 1491 priv->duplexity = 0; 1492 1493 return 0; 1494 } 1495 1496 struct phy_info phy_info_dp83865 = { 1497 0x20005c7, 1498 "NatSemi DP83865", 1499 4, 1500 (struct phy_cmd[]){ /* config */ 1501 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1502 {miim_end,} 1503 }, 1504 (struct phy_cmd[]){ /* startup */ 1505 /* Status is read once to clear old link state */ 1506 {MIIM_STATUS, miim_read, NULL}, 1507 /* Auto-negotiate */ 1508 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1509 /* Read the link and auto-neg status */ 1510 {MIIM_DP83865_LANR, miim_read, 1511 &mii_parse_dp83865_lanr}, 1512 {miim_end,} 1513 }, 1514 (struct phy_cmd[]){ /* shutdown */ 1515 {miim_end,} 1516 }, 1517 }; 1518 1519 struct phy_info phy_info_rtl8211b = { 1520 0x001cc91, 1521 "RealTek RTL8211B", 1522 4, 1523 (struct phy_cmd[]){ /* config */ 1524 /* Reset and configure the PHY */ 1525 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1526 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1527 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1528 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1529 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1530 {miim_end,} 1531 }, 1532 (struct phy_cmd[]){ /* startup */ 1533 /* Status is read once to clear old link state */ 1534 {MIIM_STATUS, miim_read, NULL}, 1535 /* Auto-negotiate */ 1536 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1537 /* Read the status */ 1538 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1539 {miim_end,} 1540 }, 1541 (struct phy_cmd[]){ /* shutdown */ 1542 {miim_end,} 1543 }, 1544 }; 1545 1546 struct phy_info *phy_info[] = { 1547 &phy_info_cis8204, 1548 &phy_info_cis8201, 1549 &phy_info_BCM5461S, 1550 &phy_info_BCM5464S, 1551 &phy_info_M88E1011S, 1552 &phy_info_M88E1111S, 1553 &phy_info_M88E1118, 1554 &phy_info_M88E1121R, 1555 &phy_info_M88E1145, 1556 &phy_info_M88E1149S, 1557 &phy_info_dm9161, 1558 &phy_info_lxt971, 1559 &phy_info_VSC8244, 1560 &phy_info_VSC8601, 1561 &phy_info_dp83865, 1562 &phy_info_rtl8211b, 1563 &phy_info_generic, 1564 NULL 1565 }; 1566 1567 /* Grab the identifier of the device's PHY, and search through 1568 * all of the known PHYs to see if one matches. If so, return 1569 * it, if not, return NULL 1570 */ 1571 struct phy_info *get_phy_info(struct eth_device *dev) 1572 { 1573 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1574 uint phy_reg, phy_ID; 1575 int i; 1576 struct phy_info *theInfo = NULL; 1577 1578 /* Grab the bits from PHYIR1, and put them in the upper half */ 1579 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1580 phy_ID = (phy_reg & 0xffff) << 16; 1581 1582 /* Grab the bits from PHYIR2, and put them in the lower half */ 1583 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1584 phy_ID |= (phy_reg & 0xffff); 1585 1586 /* loop through all the known PHY types, and find one that */ 1587 /* matches the ID we read from the PHY. */ 1588 for (i = 0; phy_info[i]; i++) { 1589 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1590 theInfo = phy_info[i]; 1591 break; 1592 } 1593 } 1594 1595 if (theInfo == NULL) { 1596 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1597 return NULL; 1598 } else { 1599 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1600 } 1601 1602 return theInfo; 1603 } 1604 1605 /* Execute the given series of commands on the given device's 1606 * PHY, running functions as necessary 1607 */ 1608 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1609 { 1610 int i; 1611 uint result; 1612 volatile tsec_t *phyregs = priv->phyregs; 1613 1614 phyregs->miimcfg = MIIMCFG_RESET; 1615 1616 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1617 1618 while (phyregs->miimind & MIIMIND_BUSY) ; 1619 1620 for (i = 0; cmd->mii_reg != miim_end; i++) { 1621 if (cmd->mii_data == miim_read) { 1622 result = read_phy_reg(priv, cmd->mii_reg); 1623 1624 if (cmd->funct != NULL) 1625 (*(cmd->funct)) (result, priv); 1626 1627 } else { 1628 if (cmd->funct != NULL) 1629 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1630 else 1631 result = cmd->mii_data; 1632 1633 write_phy_reg(priv, cmd->mii_reg, result); 1634 1635 } 1636 cmd++; 1637 } 1638 } 1639 1640 /* Relocate the function pointers in the phy cmd lists */ 1641 static void relocate_cmds(void) 1642 { 1643 struct phy_cmd **cmdlistptr; 1644 struct phy_cmd *cmd; 1645 int i, j, k; 1646 1647 for (i = 0; phy_info[i]; i++) { 1648 /* First thing's first: relocate the pointers to the 1649 * PHY command structures (the structs were done) */ 1650 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1651 + gd->reloc_off); 1652 phy_info[i]->name += gd->reloc_off; 1653 phy_info[i]->config = 1654 (struct phy_cmd *)((uint) phy_info[i]->config 1655 + gd->reloc_off); 1656 phy_info[i]->startup = 1657 (struct phy_cmd *)((uint) phy_info[i]->startup 1658 + gd->reloc_off); 1659 phy_info[i]->shutdown = 1660 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1661 + gd->reloc_off); 1662 1663 cmdlistptr = &phy_info[i]->config; 1664 j = 0; 1665 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1666 k = 0; 1667 for (cmd = *cmdlistptr; 1668 cmd->mii_reg != miim_end; 1669 cmd++) { 1670 /* Only relocate non-NULL pointers */ 1671 if (cmd->funct) 1672 cmd->funct += gd->reloc_off; 1673 1674 k++; 1675 } 1676 j++; 1677 } 1678 } 1679 1680 relocated = 1; 1681 } 1682 1683 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1684 && !defined(BITBANGMII) 1685 1686 /* 1687 * Read a MII PHY register. 1688 * 1689 * Returns: 1690 * 0 on success 1691 */ 1692 static int tsec_miiphy_read(char *devname, unsigned char addr, 1693 unsigned char reg, unsigned short *value) 1694 { 1695 unsigned short ret; 1696 struct tsec_private *priv = privlist[0]; 1697 1698 if (NULL == priv) { 1699 printf("Can't read PHY at address %d\n", addr); 1700 return -1; 1701 } 1702 1703 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1704 *value = ret; 1705 1706 return 0; 1707 } 1708 1709 /* 1710 * Write a MII PHY register. 1711 * 1712 * Returns: 1713 * 0 on success 1714 */ 1715 static int tsec_miiphy_write(char *devname, unsigned char addr, 1716 unsigned char reg, unsigned short value) 1717 { 1718 struct tsec_private *priv = privlist[0]; 1719 1720 if (NULL == priv) { 1721 printf("Can't write PHY at address %d\n", addr); 1722 return -1; 1723 } 1724 1725 write_any_phy_reg(priv, addr, reg, value); 1726 1727 return 0; 1728 } 1729 1730 #endif 1731 1732 #ifdef CONFIG_MCAST_TFTP 1733 1734 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1735 1736 /* Set the appropriate hash bit for the given addr */ 1737 1738 /* The algorithm works like so: 1739 * 1) Take the Destination Address (ie the multicast address), and 1740 * do a CRC on it (little endian), and reverse the bits of the 1741 * result. 1742 * 2) Use the 8 most significant bits as a hash into a 256-entry 1743 * table. The table is controlled through 8 32-bit registers: 1744 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1745 * gaddr7. This means that the 3 most significant bits in the 1746 * hash index which gaddr register to use, and the 5 other bits 1747 * indicate which bit (assuming an IBM numbering scheme, which 1748 * for PowerPC (tm) is usually the case) in the tregister holds 1749 * the entry. */ 1750 static int 1751 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1752 { 1753 struct tsec_private *priv = privlist[1]; 1754 volatile tsec_t *regs = priv->regs; 1755 volatile u32 *reg_array, value; 1756 u8 result, whichbit, whichreg; 1757 1758 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1759 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1760 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1761 value = (1 << (31-whichbit)); 1762 1763 reg_array = &(regs->hash.gaddr0); 1764 1765 if (set) { 1766 reg_array[whichreg] |= value; 1767 } else { 1768 reg_array[whichreg] &= ~value; 1769 } 1770 return 0; 1771 } 1772 #endif /* Multicast TFTP ? */ 1773