1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 /* The tsec_info structure contains 3 values which the 36 * driver uses to determine how to operate a given ethernet 37 * device. The information needed is: 38 * phyaddr - The address of the PHY which is attached to 39 * the given device. 40 * 41 * flags - This variable indicates whether the device 42 * supports gigabit speed ethernet, and whether it should be 43 * in reduced mode. 44 * 45 * phyregidx - This variable specifies which ethernet device 46 * controls the MII Management registers which are connected 47 * to the PHY. For now, only TSEC1 (index 0) has 48 * access to the PHYs, so all of the entries have "0". 49 * 50 * The values specified in the table are taken from the board's 51 * config file in include/configs/. When implementing a new 52 * board with ethernet capability, it is necessary to define: 53 * TSECn_PHY_ADDR 54 * TSECn_PHYIDX 55 * 56 * for n = 1,2,3, etc. And for FEC: 57 * FEC_PHY_ADDR 58 * FEC_PHYIDX 59 */ 60 static struct tsec_info_struct tsec_info[] = { 61 #ifdef CONFIG_TSEC1 62 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, 63 #else 64 {0, 0, 0}, 65 #endif 66 #ifdef CONFIG_TSEC2 67 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, 68 #else 69 {0, 0, 0}, 70 #endif 71 #ifdef CONFIG_MPC85XX_FEC 72 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, 73 #else 74 #ifdef CONFIG_TSEC3 75 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, 76 #else 77 {0, 0, 0}, 78 #endif 79 #ifdef CONFIG_TSEC4 80 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, 81 #else 82 {0, 0, 0}, 83 #endif /* CONFIG_TSEC4 */ 84 #endif /* CONFIG_MPC85XX_FEC */ 85 }; 86 87 #define MAXCONTROLLERS (4) 88 89 static int relocated = 0; 90 91 static struct tsec_private *privlist[MAXCONTROLLERS]; 92 93 #ifdef __GNUC__ 94 static RTXBD rtx __attribute__ ((aligned(8))); 95 #else 96 #error "rtx must be 64-bit aligned" 97 #endif 98 99 static int tsec_send(struct eth_device *dev, 100 volatile void *packet, int length); 101 static int tsec_recv(struct eth_device *dev); 102 static int tsec_init(struct eth_device *dev, bd_t * bd); 103 static void tsec_halt(struct eth_device *dev); 104 static void init_registers(volatile tsec_t * regs); 105 static void startup_tsec(struct eth_device *dev); 106 static int init_phy(struct eth_device *dev); 107 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 108 uint read_phy_reg(struct tsec_private *priv, uint regnum); 109 struct phy_info *get_phy_info(struct eth_device *dev); 110 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 111 static void adjust_link(struct eth_device *dev); 112 static void relocate_cmds(void); 113 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 114 && !defined(BITBANGMII) 115 static int tsec_miiphy_write(char *devname, unsigned char addr, 116 unsigned char reg, unsigned short value); 117 static int tsec_miiphy_read(char *devname, unsigned char addr, 118 unsigned char reg, unsigned short *value); 119 #endif 120 #ifdef CONFIG_MCAST_TFTP 121 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 122 #endif 123 124 /* Initialize device structure. Returns success if PHY 125 * initialization succeeded (i.e. if it recognizes the PHY) 126 */ 127 int tsec_initialize(bd_t * bis, int index, char *devname) 128 { 129 struct eth_device *dev; 130 int i; 131 struct tsec_private *priv; 132 133 dev = (struct eth_device *)malloc(sizeof *dev); 134 135 if (NULL == dev) 136 return 0; 137 138 memset(dev, 0, sizeof *dev); 139 140 priv = (struct tsec_private *)malloc(sizeof(*priv)); 141 142 if (NULL == priv) 143 return 0; 144 145 privlist[index] = priv; 146 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); 147 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + 148 tsec_info[index].phyregidx * 149 TSEC_SIZE); 150 151 priv->phyaddr = tsec_info[index].phyaddr; 152 priv->flags = tsec_info[index].flags; 153 154 sprintf(dev->name, devname); 155 dev->iobase = 0; 156 dev->priv = priv; 157 dev->init = tsec_init; 158 dev->halt = tsec_halt; 159 dev->send = tsec_send; 160 dev->recv = tsec_recv; 161 #ifdef CONFIG_MCAST_TFTP 162 dev->mcast = tsec_mcast_addr; 163 #endif 164 165 /* Tell u-boot to get the addr from the env */ 166 for (i = 0; i < 6; i++) 167 dev->enetaddr[i] = 0; 168 169 eth_register(dev); 170 171 /* Reset the MAC */ 172 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 173 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 174 175 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 176 && !defined(BITBANGMII) 177 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 178 #endif 179 180 /* Try to initialize PHY here, and return */ 181 return init_phy(dev); 182 } 183 184 /* Initializes data structures and registers for the controller, 185 * and brings the interface up. Returns the link status, meaning 186 * that it returns success if the link is up, failure otherwise. 187 * This allows u-boot to find the first active controller. 188 */ 189 int tsec_init(struct eth_device *dev, bd_t * bd) 190 { 191 uint tempval; 192 char tmpbuf[MAC_ADDR_LEN]; 193 int i; 194 struct tsec_private *priv = (struct tsec_private *)dev->priv; 195 volatile tsec_t *regs = priv->regs; 196 197 /* Make sure the controller is stopped */ 198 tsec_halt(dev); 199 200 /* Init MACCFG2. Defaults to GMII */ 201 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 202 203 /* Init ECNTRL */ 204 regs->ecntrl = ECNTRL_INIT_SETTINGS; 205 206 /* Copy the station address into the address registers. 207 * Backwards, because little endian MACS are dumb */ 208 for (i = 0; i < MAC_ADDR_LEN; i++) { 209 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 210 } 211 regs->macstnaddr1 = *((uint *) (tmpbuf)); 212 213 tempval = *((uint *) (tmpbuf + 4)); 214 215 regs->macstnaddr2 = tempval; 216 217 /* reset the indices to zero */ 218 rxIdx = 0; 219 txIdx = 0; 220 221 /* Clear out (for the most part) the other registers */ 222 init_registers(regs); 223 224 /* Ready the device for tx/rx */ 225 startup_tsec(dev); 226 227 /* If there's no link, fail */ 228 return (priv->link ? 0 : -1); 229 230 } 231 232 /* Write value to the device's PHY through the registers 233 * specified in priv, modifying the register specified in regnum. 234 * It will wait for the write to be done (or for a timeout to 235 * expire) before exiting 236 */ 237 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 238 { 239 volatile tsec_t *regbase = priv->phyregs; 240 int timeout = 1000000; 241 242 regbase->miimadd = (phyid << 8) | regnum; 243 regbase->miimcon = value; 244 asm("sync"); 245 246 timeout = 1000000; 247 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 248 } 249 250 /* #define to provide old write_phy_reg functionality without duplicating code */ 251 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 252 253 /* Reads register regnum on the device's PHY through the 254 * registers specified in priv. It lowers and raises the read 255 * command, and waits for the data to become valid (miimind 256 * notvalid bit cleared), and the bus to cease activity (miimind 257 * busy bit cleared), and then returns the value 258 */ 259 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 260 { 261 uint value; 262 volatile tsec_t *regbase = priv->phyregs; 263 264 /* Put the address of the phy, and the register 265 * number into MIIMADD */ 266 regbase->miimadd = (phyid << 8) | regnum; 267 268 /* Clear the command register, and wait */ 269 regbase->miimcom = 0; 270 asm("sync"); 271 272 /* Initiate a read command, and wait */ 273 regbase->miimcom = MIIM_READ_COMMAND; 274 asm("sync"); 275 276 /* Wait for the the indication that the read is done */ 277 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 278 279 /* Grab the value read from the PHY */ 280 value = regbase->miimstat; 281 282 return value; 283 } 284 285 /* #define to provide old read_phy_reg functionality without duplicating code */ 286 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 287 288 /* Discover which PHY is attached to the device, and configure it 289 * properly. If the PHY is not recognized, then return 0 290 * (failure). Otherwise, return 1 291 */ 292 static int init_phy(struct eth_device *dev) 293 { 294 struct tsec_private *priv = (struct tsec_private *)dev->priv; 295 struct phy_info *curphy; 296 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 297 298 /* Assign a Physical address to the TBI */ 299 regs->tbipa = CFG_TBIPA_VALUE; 300 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 301 regs->tbipa = CFG_TBIPA_VALUE; 302 asm("sync"); 303 304 /* Reset MII (due to new addresses) */ 305 priv->phyregs->miimcfg = MIIMCFG_RESET; 306 asm("sync"); 307 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 308 asm("sync"); 309 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 310 311 if (0 == relocated) 312 relocate_cmds(); 313 314 /* Get the cmd structure corresponding to the attached 315 * PHY */ 316 curphy = get_phy_info(dev); 317 318 if (curphy == NULL) { 319 priv->phyinfo = NULL; 320 printf("%s: No PHY found\n", dev->name); 321 322 return 0; 323 } 324 325 priv->phyinfo = curphy; 326 327 phy_run_commands(priv, priv->phyinfo->config); 328 329 return 1; 330 } 331 332 /* 333 * Returns which value to write to the control register. 334 * For 10/100, the value is slightly different 335 */ 336 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 337 { 338 if (priv->flags & TSEC_GIGABIT) 339 return MIIM_CONTROL_INIT; 340 else 341 return MIIM_CR_INIT; 342 } 343 344 /* Parse the status register for link, and then do 345 * auto-negotiation 346 */ 347 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 348 { 349 /* 350 * Wait if the link is up, and autonegotiation is in progress 351 * (ie - we're capable and it's not done) 352 */ 353 mii_reg = read_phy_reg(priv, MIIM_STATUS); 354 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 355 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 356 int i = 0; 357 358 puts("Waiting for PHY auto negotiation to complete"); 359 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 360 /* 361 * Timeout reached ? 362 */ 363 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 364 puts(" TIMEOUT !\n"); 365 priv->link = 0; 366 return 0; 367 } 368 369 if ((i++ % 1000) == 0) { 370 putc('.'); 371 } 372 udelay(1000); /* 1 ms */ 373 mii_reg = read_phy_reg(priv, MIIM_STATUS); 374 } 375 puts(" done\n"); 376 priv->link = 1; 377 udelay(500000); /* another 500 ms (results in faster booting) */ 378 } else { 379 if (mii_reg & MIIM_STATUS_LINK) 380 priv->link = 1; 381 else 382 priv->link = 0; 383 } 384 385 return 0; 386 } 387 388 /* Generic function which updates the speed and duplex. If 389 * autonegotiation is enabled, it uses the AND of the link 390 * partner's advertised capabilities and our advertised 391 * capabilities. If autonegotiation is disabled, we use the 392 * appropriate bits in the control register. 393 * 394 * Stolen from Linux's mii.c and phy_device.c 395 */ 396 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 397 { 398 /* We're using autonegotiation */ 399 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 400 uint lpa = 0; 401 uint gblpa = 0; 402 403 /* Check for gigabit capability */ 404 if (mii_reg & PHY_BMSR_EXT) { 405 /* We want a list of states supported by 406 * both PHYs in the link 407 */ 408 gblpa = read_phy_reg(priv, PHY_1000BTSR); 409 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 410 } 411 412 /* Set the baseline so we only have to set them 413 * if they're different 414 */ 415 priv->speed = 10; 416 priv->duplexity = 0; 417 418 /* Check the gigabit fields */ 419 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 420 priv->speed = 1000; 421 422 if (gblpa & PHY_1000BTSR_1000FD) 423 priv->duplexity = 1; 424 425 /* We're done! */ 426 return 0; 427 } 428 429 lpa = read_phy_reg(priv, PHY_ANAR); 430 lpa &= read_phy_reg(priv, PHY_ANLPAR); 431 432 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 433 priv->speed = 100; 434 435 if (lpa & PHY_ANLPAR_TXFD) 436 priv->duplexity = 1; 437 438 } else if (lpa & PHY_ANLPAR_10FD) 439 priv->duplexity = 1; 440 } else { 441 uint bmcr = read_phy_reg(priv, PHY_BMCR); 442 443 priv->speed = 10; 444 priv->duplexity = 0; 445 446 if (bmcr & PHY_BMCR_DPLX) 447 priv->duplexity = 1; 448 449 if (bmcr & PHY_BMCR_1000_MBPS) 450 priv->speed = 1000; 451 else if (bmcr & PHY_BMCR_100_MBPS) 452 priv->speed = 100; 453 } 454 455 return 0; 456 } 457 458 /* 459 * Parse the BCM54xx status register for speed and duplex information. 460 * The linux sungem_phy has this information, but in a table format. 461 */ 462 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 463 { 464 465 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 466 467 case 1: 468 printf("Enet starting in 10BT/HD\n"); 469 priv->duplexity = 0; 470 priv->speed = 10; 471 break; 472 473 case 2: 474 printf("Enet starting in 10BT/FD\n"); 475 priv->duplexity = 1; 476 priv->speed = 10; 477 break; 478 479 case 3: 480 printf("Enet starting in 100BT/HD\n"); 481 priv->duplexity = 0; 482 priv->speed = 100; 483 break; 484 485 case 5: 486 printf("Enet starting in 100BT/FD\n"); 487 priv->duplexity = 1; 488 priv->speed = 100; 489 break; 490 491 case 6: 492 printf("Enet starting in 1000BT/HD\n"); 493 priv->duplexity = 0; 494 priv->speed = 1000; 495 break; 496 497 case 7: 498 printf("Enet starting in 1000BT/FD\n"); 499 priv->duplexity = 1; 500 priv->speed = 1000; 501 break; 502 503 default: 504 printf("Auto-neg error, defaulting to 10BT/HD\n"); 505 priv->duplexity = 0; 506 priv->speed = 10; 507 break; 508 } 509 510 return 0; 511 512 } 513 /* Parse the 88E1011's status register for speed and duplex 514 * information 515 */ 516 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 517 { 518 uint speed; 519 520 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 521 522 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 523 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 524 int i = 0; 525 526 puts("Waiting for PHY realtime link"); 527 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 528 /* Timeout reached ? */ 529 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 530 puts(" TIMEOUT !\n"); 531 priv->link = 0; 532 break; 533 } 534 535 if ((i++ % 1000) == 0) { 536 putc('.'); 537 } 538 udelay(1000); /* 1 ms */ 539 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 540 } 541 puts(" done\n"); 542 udelay(500000); /* another 500 ms (results in faster booting) */ 543 } else { 544 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 545 priv->link = 1; 546 else 547 priv->link = 0; 548 } 549 550 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 551 priv->duplexity = 1; 552 else 553 priv->duplexity = 0; 554 555 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 556 557 switch (speed) { 558 case MIIM_88E1011_PHYSTAT_GBIT: 559 priv->speed = 1000; 560 break; 561 case MIIM_88E1011_PHYSTAT_100: 562 priv->speed = 100; 563 break; 564 default: 565 priv->speed = 10; 566 } 567 568 return 0; 569 } 570 571 /* Parse the RTL8211B's status register for speed and duplex 572 * information 573 */ 574 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 575 { 576 uint speed; 577 578 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 579 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 580 int i = 0; 581 582 /* in case of timeout ->link is cleared */ 583 priv->link = 1; 584 puts("Waiting for PHY realtime link"); 585 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 586 /* Timeout reached ? */ 587 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 588 puts(" TIMEOUT !\n"); 589 priv->link = 0; 590 break; 591 } 592 593 if ((i++ % 1000) == 0) { 594 putc('.'); 595 } 596 udelay(1000); /* 1 ms */ 597 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 598 } 599 puts(" done\n"); 600 udelay(500000); /* another 500 ms (results in faster booting) */ 601 } else { 602 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 603 priv->link = 1; 604 else 605 priv->link = 0; 606 } 607 608 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 609 priv->duplexity = 1; 610 else 611 priv->duplexity = 0; 612 613 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 614 615 switch (speed) { 616 case MIIM_RTL8211B_PHYSTAT_GBIT: 617 priv->speed = 1000; 618 break; 619 case MIIM_RTL8211B_PHYSTAT_100: 620 priv->speed = 100; 621 break; 622 default: 623 priv->speed = 10; 624 } 625 626 return 0; 627 } 628 629 /* Parse the cis8201's status register for speed and duplex 630 * information 631 */ 632 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 633 { 634 uint speed; 635 636 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 637 priv->duplexity = 1; 638 else 639 priv->duplexity = 0; 640 641 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 642 switch (speed) { 643 case MIIM_CIS8201_AUXCONSTAT_GBIT: 644 priv->speed = 1000; 645 break; 646 case MIIM_CIS8201_AUXCONSTAT_100: 647 priv->speed = 100; 648 break; 649 default: 650 priv->speed = 10; 651 break; 652 } 653 654 return 0; 655 } 656 657 /* Parse the vsc8244's status register for speed and duplex 658 * information 659 */ 660 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 661 { 662 uint speed; 663 664 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 665 priv->duplexity = 1; 666 else 667 priv->duplexity = 0; 668 669 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 670 switch (speed) { 671 case MIIM_VSC8244_AUXCONSTAT_GBIT: 672 priv->speed = 1000; 673 break; 674 case MIIM_VSC8244_AUXCONSTAT_100: 675 priv->speed = 100; 676 break; 677 default: 678 priv->speed = 10; 679 break; 680 } 681 682 return 0; 683 } 684 685 /* Parse the DM9161's status register for speed and duplex 686 * information 687 */ 688 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 689 { 690 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 691 priv->speed = 100; 692 else 693 priv->speed = 10; 694 695 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 696 priv->duplexity = 1; 697 else 698 priv->duplexity = 0; 699 700 return 0; 701 } 702 703 /* 704 * Hack to write all 4 PHYs with the LED values 705 */ 706 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 707 { 708 uint phyid; 709 volatile tsec_t *regbase = priv->phyregs; 710 int timeout = 1000000; 711 712 for (phyid = 0; phyid < 4; phyid++) { 713 regbase->miimadd = (phyid << 8) | mii_reg; 714 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 715 asm("sync"); 716 717 timeout = 1000000; 718 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 719 } 720 721 return MIIM_CIS8204_SLEDCON_INIT; 722 } 723 724 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 725 { 726 if (priv->flags & TSEC_REDUCED) 727 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 728 else 729 return MIIM_CIS8204_EPHYCON_INIT; 730 } 731 732 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 733 { 734 uint mii_data = read_phy_reg(priv, mii_reg); 735 736 if (priv->flags & TSEC_REDUCED) 737 mii_data = (mii_data & 0xfff0) | 0x000b; 738 return mii_data; 739 } 740 741 /* Initialized required registers to appropriate values, zeroing 742 * those we don't care about (unless zero is bad, in which case, 743 * choose a more appropriate value) 744 */ 745 static void init_registers(volatile tsec_t * regs) 746 { 747 /* Clear IEVENT */ 748 regs->ievent = IEVENT_INIT_CLEAR; 749 750 regs->imask = IMASK_INIT_CLEAR; 751 752 regs->hash.iaddr0 = 0; 753 regs->hash.iaddr1 = 0; 754 regs->hash.iaddr2 = 0; 755 regs->hash.iaddr3 = 0; 756 regs->hash.iaddr4 = 0; 757 regs->hash.iaddr5 = 0; 758 regs->hash.iaddr6 = 0; 759 regs->hash.iaddr7 = 0; 760 761 regs->hash.gaddr0 = 0; 762 regs->hash.gaddr1 = 0; 763 regs->hash.gaddr2 = 0; 764 regs->hash.gaddr3 = 0; 765 regs->hash.gaddr4 = 0; 766 regs->hash.gaddr5 = 0; 767 regs->hash.gaddr6 = 0; 768 regs->hash.gaddr7 = 0; 769 770 regs->rctrl = 0x00000000; 771 772 /* Init RMON mib registers */ 773 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 774 775 regs->rmon.cam1 = 0xffffffff; 776 regs->rmon.cam2 = 0xffffffff; 777 778 regs->mrblr = MRBLR_INIT_SETTINGS; 779 780 regs->minflr = MINFLR_INIT_SETTINGS; 781 782 regs->attr = ATTR_INIT_SETTINGS; 783 regs->attreli = ATTRELI_INIT_SETTINGS; 784 785 } 786 787 /* Configure maccfg2 based on negotiated speed and duplex 788 * reported by PHY handling code 789 */ 790 static void adjust_link(struct eth_device *dev) 791 { 792 struct tsec_private *priv = (struct tsec_private *)dev->priv; 793 volatile tsec_t *regs = priv->regs; 794 795 if (priv->link) { 796 if (priv->duplexity != 0) 797 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 798 else 799 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 800 801 switch (priv->speed) { 802 case 1000: 803 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 804 | MACCFG2_GMII); 805 break; 806 case 100: 807 case 10: 808 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 809 | MACCFG2_MII); 810 811 /* Set R100 bit in all modes although 812 * it is only used in RGMII mode 813 */ 814 if (priv->speed == 100) 815 regs->ecntrl |= ECNTRL_R100; 816 else 817 regs->ecntrl &= ~(ECNTRL_R100); 818 break; 819 default: 820 printf("%s: Speed was bad\n", dev->name); 821 break; 822 } 823 824 printf("Speed: %d, %s duplex\n", priv->speed, 825 (priv->duplexity) ? "full" : "half"); 826 827 } else { 828 printf("%s: No link.\n", dev->name); 829 } 830 } 831 832 /* Set up the buffers and their descriptors, and bring up the 833 * interface 834 */ 835 static void startup_tsec(struct eth_device *dev) 836 { 837 int i; 838 struct tsec_private *priv = (struct tsec_private *)dev->priv; 839 volatile tsec_t *regs = priv->regs; 840 841 /* Point to the buffer descriptors */ 842 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 843 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 844 845 /* Initialize the Rx Buffer descriptors */ 846 for (i = 0; i < PKTBUFSRX; i++) { 847 rtx.rxbd[i].status = RXBD_EMPTY; 848 rtx.rxbd[i].length = 0; 849 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 850 } 851 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 852 853 /* Initialize the TX Buffer Descriptors */ 854 for (i = 0; i < TX_BUF_CNT; i++) { 855 rtx.txbd[i].status = 0; 856 rtx.txbd[i].length = 0; 857 rtx.txbd[i].bufPtr = 0; 858 } 859 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 860 861 /* Start up the PHY */ 862 if(priv->phyinfo) 863 phy_run_commands(priv, priv->phyinfo->startup); 864 865 adjust_link(dev); 866 867 /* Enable Transmit and Receive */ 868 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 869 870 /* Tell the DMA it is clear to go */ 871 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 872 regs->tstat = TSTAT_CLEAR_THALT; 873 regs->rstat = RSTAT_CLEAR_RHALT; 874 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 875 } 876 877 /* This returns the status bits of the device. The return value 878 * is never checked, and this is what the 8260 driver did, so we 879 * do the same. Presumably, this would be zero if there were no 880 * errors 881 */ 882 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 883 { 884 int i; 885 int result = 0; 886 struct tsec_private *priv = (struct tsec_private *)dev->priv; 887 volatile tsec_t *regs = priv->regs; 888 889 /* Find an empty buffer descriptor */ 890 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 891 if (i >= TOUT_LOOP) { 892 debug("%s: tsec: tx buffers full\n", dev->name); 893 return result; 894 } 895 } 896 897 rtx.txbd[txIdx].bufPtr = (uint) packet; 898 rtx.txbd[txIdx].length = length; 899 rtx.txbd[txIdx].status |= 900 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 901 902 /* Tell the DMA to go */ 903 regs->tstat = TSTAT_CLEAR_THALT; 904 905 /* Wait for buffer to be transmitted */ 906 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 907 if (i >= TOUT_LOOP) { 908 debug("%s: tsec: tx error\n", dev->name); 909 return result; 910 } 911 } 912 913 txIdx = (txIdx + 1) % TX_BUF_CNT; 914 result = rtx.txbd[txIdx].status & TXBD_STATS; 915 916 return result; 917 } 918 919 static int tsec_recv(struct eth_device *dev) 920 { 921 int length; 922 struct tsec_private *priv = (struct tsec_private *)dev->priv; 923 volatile tsec_t *regs = priv->regs; 924 925 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 926 927 length = rtx.rxbd[rxIdx].length; 928 929 /* Send the packet up if there were no errors */ 930 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 931 NetReceive(NetRxPackets[rxIdx], length - 4); 932 } else { 933 printf("Got error %x\n", 934 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 935 } 936 937 rtx.rxbd[rxIdx].length = 0; 938 939 /* Set the wrap bit if this is the last element in the list */ 940 rtx.rxbd[rxIdx].status = 941 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 942 943 rxIdx = (rxIdx + 1) % PKTBUFSRX; 944 } 945 946 if (regs->ievent & IEVENT_BSY) { 947 regs->ievent = IEVENT_BSY; 948 regs->rstat = RSTAT_CLEAR_RHALT; 949 } 950 951 return -1; 952 953 } 954 955 /* Stop the interface */ 956 static void tsec_halt(struct eth_device *dev) 957 { 958 struct tsec_private *priv = (struct tsec_private *)dev->priv; 959 volatile tsec_t *regs = priv->regs; 960 961 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 962 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 963 964 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 965 966 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 967 968 /* Shut down the PHY, as needed */ 969 if(priv->phyinfo) 970 phy_run_commands(priv, priv->phyinfo->shutdown); 971 } 972 973 struct phy_info phy_info_M88E1149S = { 974 0x1410ca, 975 "Marvell 88E1149S", 976 4, 977 (struct phy_cmd[]){ /* config */ 978 /* Reset and configure the PHY */ 979 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 980 {0x1d, 0x1f, NULL}, 981 {0x1e, 0x200c, NULL}, 982 {0x1d, 0x5, NULL}, 983 {0x1e, 0x0, NULL}, 984 {0x1e, 0x100, NULL}, 985 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 986 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 987 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 988 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 989 {miim_end,} 990 }, 991 (struct phy_cmd[]){ /* startup */ 992 /* Status is read once to clear old link state */ 993 {MIIM_STATUS, miim_read, NULL}, 994 /* Auto-negotiate */ 995 {MIIM_STATUS, miim_read, &mii_parse_sr}, 996 /* Read the status */ 997 {MIIM_88E1011_PHY_STATUS, miim_read, 998 &mii_parse_88E1011_psr}, 999 {miim_end,} 1000 }, 1001 (struct phy_cmd[]){ /* shutdown */ 1002 {miim_end,} 1003 }, 1004 }; 1005 1006 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1007 struct phy_info phy_info_BCM5461S = { 1008 0x02060c1, /* 5461 ID */ 1009 "Broadcom BCM5461S", 1010 0, /* not clear to me what minor revisions we can shift away */ 1011 (struct phy_cmd[]) { /* config */ 1012 /* Reset and configure the PHY */ 1013 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1014 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1015 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1016 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1017 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1018 {miim_end,} 1019 }, 1020 (struct phy_cmd[]) { /* startup */ 1021 /* Status is read once to clear old link state */ 1022 {MIIM_STATUS, miim_read, NULL}, 1023 /* Auto-negotiate */ 1024 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1025 /* Read the status */ 1026 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1027 {miim_end,} 1028 }, 1029 (struct phy_cmd[]) { /* shutdown */ 1030 {miim_end,} 1031 }, 1032 }; 1033 1034 struct phy_info phy_info_BCM5464S = { 1035 0x02060b1, /* 5464 ID */ 1036 "Broadcom BCM5464S", 1037 0, /* not clear to me what minor revisions we can shift away */ 1038 (struct phy_cmd[]) { /* config */ 1039 /* Reset and configure the PHY */ 1040 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1041 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1042 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1043 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1044 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1045 {miim_end,} 1046 }, 1047 (struct phy_cmd[]) { /* startup */ 1048 /* Status is read once to clear old link state */ 1049 {MIIM_STATUS, miim_read, NULL}, 1050 /* Auto-negotiate */ 1051 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1052 /* Read the status */ 1053 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1054 {miim_end,} 1055 }, 1056 (struct phy_cmd[]) { /* shutdown */ 1057 {miim_end,} 1058 }, 1059 }; 1060 1061 struct phy_info phy_info_M88E1011S = { 1062 0x01410c6, 1063 "Marvell 88E1011S", 1064 4, 1065 (struct phy_cmd[]){ /* config */ 1066 /* Reset and configure the PHY */ 1067 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1068 {0x1d, 0x1f, NULL}, 1069 {0x1e, 0x200c, NULL}, 1070 {0x1d, 0x5, NULL}, 1071 {0x1e, 0x0, NULL}, 1072 {0x1e, 0x100, NULL}, 1073 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1074 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1075 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1076 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1077 {miim_end,} 1078 }, 1079 (struct phy_cmd[]){ /* startup */ 1080 /* Status is read once to clear old link state */ 1081 {MIIM_STATUS, miim_read, NULL}, 1082 /* Auto-negotiate */ 1083 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1084 /* Read the status */ 1085 {MIIM_88E1011_PHY_STATUS, miim_read, 1086 &mii_parse_88E1011_psr}, 1087 {miim_end,} 1088 }, 1089 (struct phy_cmd[]){ /* shutdown */ 1090 {miim_end,} 1091 }, 1092 }; 1093 1094 struct phy_info phy_info_M88E1111S = { 1095 0x01410cc, 1096 "Marvell 88E1111S", 1097 4, 1098 (struct phy_cmd[]){ /* config */ 1099 /* Reset and configure the PHY */ 1100 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1101 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1102 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1103 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1104 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1105 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1106 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1107 {miim_end,} 1108 }, 1109 (struct phy_cmd[]){ /* startup */ 1110 /* Status is read once to clear old link state */ 1111 {MIIM_STATUS, miim_read, NULL}, 1112 /* Auto-negotiate */ 1113 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1114 /* Read the status */ 1115 {MIIM_88E1011_PHY_STATUS, miim_read, 1116 &mii_parse_88E1011_psr}, 1117 {miim_end,} 1118 }, 1119 (struct phy_cmd[]){ /* shutdown */ 1120 {miim_end,} 1121 }, 1122 }; 1123 1124 struct phy_info phy_info_M88E1118 = { 1125 0x01410e1, 1126 "Marvell 88E1118", 1127 4, 1128 (struct phy_cmd[]){ /* config */ 1129 /* Reset and configure the PHY */ 1130 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1131 {0x16, 0x0002, NULL}, /* Change Page Number */ 1132 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1133 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1134 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1135 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1136 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1137 {miim_end,} 1138 }, 1139 (struct phy_cmd[]){ /* startup */ 1140 {0x16, 0x0000, NULL}, /* Change Page Number */ 1141 /* Status is read once to clear old link state */ 1142 {MIIM_STATUS, miim_read, NULL}, 1143 /* Auto-negotiate */ 1144 /* Read the status */ 1145 {MIIM_88E1011_PHY_STATUS, miim_read, 1146 &mii_parse_88E1011_psr}, 1147 {miim_end,} 1148 }, 1149 (struct phy_cmd[]){ /* shutdown */ 1150 {miim_end,} 1151 }, 1152 }; 1153 1154 /* 1155 * Since to access LED register we need do switch the page, we 1156 * do LED configuring in the miim_read-like function as follows 1157 */ 1158 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1159 { 1160 uint pg; 1161 1162 /* Switch the page to access the led register */ 1163 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1164 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1165 1166 /* Configure leds */ 1167 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1168 MIIM_88E1121_PHY_LED_DEF); 1169 1170 /* Restore the page pointer */ 1171 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1172 return 0; 1173 } 1174 1175 struct phy_info phy_info_M88E1121R = { 1176 0x01410cb, 1177 "Marvell 88E1121R", 1178 4, 1179 (struct phy_cmd[]){ /* config */ 1180 /* Reset and configure the PHY */ 1181 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1182 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1183 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1184 /* Configure leds */ 1185 {MIIM_88E1121_PHY_LED_CTRL, miim_read, 1186 &mii_88E1121_set_led}, 1187 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1188 {miim_end,} 1189 }, 1190 (struct phy_cmd[]){ /* startup */ 1191 /* Status is read once to clear old link state */ 1192 {MIIM_STATUS, miim_read, NULL}, 1193 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1194 {MIIM_STATUS, miim_read, &mii_parse_link}, 1195 {miim_end,} 1196 }, 1197 (struct phy_cmd[]){ /* shutdown */ 1198 {miim_end,} 1199 }, 1200 }; 1201 1202 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1203 { 1204 uint mii_data = read_phy_reg(priv, mii_reg); 1205 1206 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1207 if (priv->flags & TSEC_REDUCED) 1208 return mii_data | 1209 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1210 else 1211 return mii_data; 1212 } 1213 1214 static struct phy_info phy_info_M88E1145 = { 1215 0x01410cd, 1216 "Marvell 88E1145", 1217 4, 1218 (struct phy_cmd[]){ /* config */ 1219 /* Reset the PHY */ 1220 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1221 1222 /* Errata E0, E1 */ 1223 {29, 0x001b, NULL}, 1224 {30, 0x418f, NULL}, 1225 {29, 0x0016, NULL}, 1226 {30, 0xa2da, NULL}, 1227 1228 /* Configure the PHY */ 1229 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1230 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1231 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1232 NULL}, 1233 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1234 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1235 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1236 {miim_end,} 1237 }, 1238 (struct phy_cmd[]){ /* startup */ 1239 /* Status is read once to clear old link state */ 1240 {MIIM_STATUS, miim_read, NULL}, 1241 /* Auto-negotiate */ 1242 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1243 {MIIM_88E1111_PHY_LED_CONTROL, 1244 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1245 /* Read the Status */ 1246 {MIIM_88E1011_PHY_STATUS, miim_read, 1247 &mii_parse_88E1011_psr}, 1248 {miim_end,} 1249 }, 1250 (struct phy_cmd[]){ /* shutdown */ 1251 {miim_end,} 1252 }, 1253 }; 1254 1255 struct phy_info phy_info_cis8204 = { 1256 0x3f11, 1257 "Cicada Cis8204", 1258 6, 1259 (struct phy_cmd[]){ /* config */ 1260 /* Override PHY config settings */ 1261 {MIIM_CIS8201_AUX_CONSTAT, 1262 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1263 /* Configure some basic stuff */ 1264 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1265 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1266 &mii_cis8204_fixled}, 1267 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1268 &mii_cis8204_setmode}, 1269 {miim_end,} 1270 }, 1271 (struct phy_cmd[]){ /* startup */ 1272 /* Read the Status (2x to make sure link is right) */ 1273 {MIIM_STATUS, miim_read, NULL}, 1274 /* Auto-negotiate */ 1275 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1276 /* Read the status */ 1277 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1278 &mii_parse_cis8201}, 1279 {miim_end,} 1280 }, 1281 (struct phy_cmd[]){ /* shutdown */ 1282 {miim_end,} 1283 }, 1284 }; 1285 1286 /* Cicada 8201 */ 1287 struct phy_info phy_info_cis8201 = { 1288 0xfc41, 1289 "CIS8201", 1290 4, 1291 (struct phy_cmd[]){ /* config */ 1292 /* Override PHY config settings */ 1293 {MIIM_CIS8201_AUX_CONSTAT, 1294 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1295 /* Set up the interface mode */ 1296 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1297 NULL}, 1298 /* Configure some basic stuff */ 1299 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1300 {miim_end,} 1301 }, 1302 (struct phy_cmd[]){ /* startup */ 1303 /* Read the Status (2x to make sure link is right) */ 1304 {MIIM_STATUS, miim_read, NULL}, 1305 /* Auto-negotiate */ 1306 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1307 /* Read the status */ 1308 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1309 &mii_parse_cis8201}, 1310 {miim_end,} 1311 }, 1312 (struct phy_cmd[]){ /* shutdown */ 1313 {miim_end,} 1314 }, 1315 }; 1316 struct phy_info phy_info_VSC8244 = { 1317 0x3f1b, 1318 "Vitesse VSC8244", 1319 6, 1320 (struct phy_cmd[]){ /* config */ 1321 /* Override PHY config settings */ 1322 /* Configure some basic stuff */ 1323 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1324 {miim_end,} 1325 }, 1326 (struct phy_cmd[]){ /* startup */ 1327 /* Read the Status (2x to make sure link is right) */ 1328 {MIIM_STATUS, miim_read, NULL}, 1329 /* Auto-negotiate */ 1330 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1331 /* Read the status */ 1332 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1333 &mii_parse_vsc8244}, 1334 {miim_end,} 1335 }, 1336 (struct phy_cmd[]){ /* shutdown */ 1337 {miim_end,} 1338 }, 1339 }; 1340 1341 struct phy_info phy_info_VSC8601 = { 1342 0x00007042, 1343 "Vitesse VSC8601", 1344 4, 1345 (struct phy_cmd[]){ /* config */ 1346 /* Override PHY config settings */ 1347 /* Configure some basic stuff */ 1348 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1349 #ifdef CFG_VSC8601_SKEWFIX 1350 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1351 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) 1352 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1353 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) 1354 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1355 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1356 #endif 1357 #endif 1358 {miim_end,} 1359 }, 1360 (struct phy_cmd[]){ /* startup */ 1361 /* Read the Status (2x to make sure link is right) */ 1362 {MIIM_STATUS, miim_read, NULL}, 1363 /* Auto-negotiate */ 1364 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1365 /* Read the status */ 1366 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1367 &mii_parse_vsc8244}, 1368 {miim_end,} 1369 }, 1370 (struct phy_cmd[]){ /* shutdown */ 1371 {miim_end,} 1372 }, 1373 }; 1374 1375 1376 struct phy_info phy_info_dm9161 = { 1377 0x0181b88, 1378 "Davicom DM9161E", 1379 4, 1380 (struct phy_cmd[]){ /* config */ 1381 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1382 /* Do not bypass the scrambler/descrambler */ 1383 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1384 /* Clear 10BTCSR to default */ 1385 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1386 NULL}, 1387 /* Configure some basic stuff */ 1388 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1389 /* Restart Auto Negotiation */ 1390 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1391 {miim_end,} 1392 }, 1393 (struct phy_cmd[]){ /* startup */ 1394 /* Status is read once to clear old link state */ 1395 {MIIM_STATUS, miim_read, NULL}, 1396 /* Auto-negotiate */ 1397 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1398 /* Read the status */ 1399 {MIIM_DM9161_SCSR, miim_read, 1400 &mii_parse_dm9161_scsr}, 1401 {miim_end,} 1402 }, 1403 (struct phy_cmd[]){ /* shutdown */ 1404 {miim_end,} 1405 }, 1406 }; 1407 /* a generic flavor. */ 1408 struct phy_info phy_info_generic = { 1409 0, 1410 "Unknown/Generic PHY", 1411 32, 1412 (struct phy_cmd[]) { /* config */ 1413 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1414 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1415 {miim_end,} 1416 }, 1417 (struct phy_cmd[]) { /* startup */ 1418 {PHY_BMSR, miim_read, NULL}, 1419 {PHY_BMSR, miim_read, &mii_parse_sr}, 1420 {PHY_BMSR, miim_read, &mii_parse_link}, 1421 {miim_end,} 1422 }, 1423 (struct phy_cmd[]) { /* shutdown */ 1424 {miim_end,} 1425 } 1426 }; 1427 1428 1429 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1430 { 1431 unsigned int speed; 1432 if (priv->link) { 1433 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1434 1435 switch (speed) { 1436 case MIIM_LXT971_SR2_10HDX: 1437 priv->speed = 10; 1438 priv->duplexity = 0; 1439 break; 1440 case MIIM_LXT971_SR2_10FDX: 1441 priv->speed = 10; 1442 priv->duplexity = 1; 1443 break; 1444 case MIIM_LXT971_SR2_100HDX: 1445 priv->speed = 100; 1446 priv->duplexity = 0; 1447 break; 1448 default: 1449 priv->speed = 100; 1450 priv->duplexity = 1; 1451 } 1452 } else { 1453 priv->speed = 0; 1454 priv->duplexity = 0; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static struct phy_info phy_info_lxt971 = { 1461 0x0001378e, 1462 "LXT971", 1463 4, 1464 (struct phy_cmd[]){ /* config */ 1465 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1466 {miim_end,} 1467 }, 1468 (struct phy_cmd[]){ /* startup - enable interrupts */ 1469 /* { 0x12, 0x00f2, NULL }, */ 1470 {MIIM_STATUS, miim_read, NULL}, 1471 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1472 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1473 {miim_end,} 1474 }, 1475 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1476 {miim_end,} 1477 }, 1478 }; 1479 1480 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1481 * information 1482 */ 1483 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1484 { 1485 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1486 1487 case MIIM_DP83865_SPD_1000: 1488 priv->speed = 1000; 1489 break; 1490 1491 case MIIM_DP83865_SPD_100: 1492 priv->speed = 100; 1493 break; 1494 1495 default: 1496 priv->speed = 10; 1497 break; 1498 1499 } 1500 1501 if (mii_reg & MIIM_DP83865_DPX_FULL) 1502 priv->duplexity = 1; 1503 else 1504 priv->duplexity = 0; 1505 1506 return 0; 1507 } 1508 1509 struct phy_info phy_info_dp83865 = { 1510 0x20005c7, 1511 "NatSemi DP83865", 1512 4, 1513 (struct phy_cmd[]){ /* config */ 1514 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1515 {miim_end,} 1516 }, 1517 (struct phy_cmd[]){ /* startup */ 1518 /* Status is read once to clear old link state */ 1519 {MIIM_STATUS, miim_read, NULL}, 1520 /* Auto-negotiate */ 1521 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1522 /* Read the link and auto-neg status */ 1523 {MIIM_DP83865_LANR, miim_read, 1524 &mii_parse_dp83865_lanr}, 1525 {miim_end,} 1526 }, 1527 (struct phy_cmd[]){ /* shutdown */ 1528 {miim_end,} 1529 }, 1530 }; 1531 1532 struct phy_info phy_info_rtl8211b = { 1533 0x001cc91, 1534 "RealTek RTL8211B", 1535 4, 1536 (struct phy_cmd[]){ /* config */ 1537 /* Reset and configure the PHY */ 1538 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1539 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1540 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1541 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1542 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1543 {miim_end,} 1544 }, 1545 (struct phy_cmd[]){ /* startup */ 1546 /* Status is read once to clear old link state */ 1547 {MIIM_STATUS, miim_read, NULL}, 1548 /* Auto-negotiate */ 1549 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1550 /* Read the status */ 1551 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1552 {miim_end,} 1553 }, 1554 (struct phy_cmd[]){ /* shutdown */ 1555 {miim_end,} 1556 }, 1557 }; 1558 1559 struct phy_info *phy_info[] = { 1560 &phy_info_cis8204, 1561 &phy_info_cis8201, 1562 &phy_info_BCM5461S, 1563 &phy_info_BCM5464S, 1564 &phy_info_M88E1011S, 1565 &phy_info_M88E1111S, 1566 &phy_info_M88E1118, 1567 &phy_info_M88E1121R, 1568 &phy_info_M88E1145, 1569 &phy_info_M88E1149S, 1570 &phy_info_dm9161, 1571 &phy_info_lxt971, 1572 &phy_info_VSC8244, 1573 &phy_info_VSC8601, 1574 &phy_info_dp83865, 1575 &phy_info_rtl8211b, 1576 &phy_info_generic, 1577 NULL 1578 }; 1579 1580 /* Grab the identifier of the device's PHY, and search through 1581 * all of the known PHYs to see if one matches. If so, return 1582 * it, if not, return NULL 1583 */ 1584 struct phy_info *get_phy_info(struct eth_device *dev) 1585 { 1586 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1587 uint phy_reg, phy_ID; 1588 int i; 1589 struct phy_info *theInfo = NULL; 1590 1591 /* Grab the bits from PHYIR1, and put them in the upper half */ 1592 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1593 phy_ID = (phy_reg & 0xffff) << 16; 1594 1595 /* Grab the bits from PHYIR2, and put them in the lower half */ 1596 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1597 phy_ID |= (phy_reg & 0xffff); 1598 1599 /* loop through all the known PHY types, and find one that */ 1600 /* matches the ID we read from the PHY. */ 1601 for (i = 0; phy_info[i]; i++) { 1602 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1603 theInfo = phy_info[i]; 1604 break; 1605 } 1606 } 1607 1608 if (theInfo == NULL) { 1609 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1610 return NULL; 1611 } else { 1612 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1613 } 1614 1615 return theInfo; 1616 } 1617 1618 /* Execute the given series of commands on the given device's 1619 * PHY, running functions as necessary 1620 */ 1621 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1622 { 1623 int i; 1624 uint result; 1625 volatile tsec_t *phyregs = priv->phyregs; 1626 1627 phyregs->miimcfg = MIIMCFG_RESET; 1628 1629 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1630 1631 while (phyregs->miimind & MIIMIND_BUSY) ; 1632 1633 for (i = 0; cmd->mii_reg != miim_end; i++) { 1634 if (cmd->mii_data == miim_read) { 1635 result = read_phy_reg(priv, cmd->mii_reg); 1636 1637 if (cmd->funct != NULL) 1638 (*(cmd->funct)) (result, priv); 1639 1640 } else { 1641 if (cmd->funct != NULL) 1642 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1643 else 1644 result = cmd->mii_data; 1645 1646 write_phy_reg(priv, cmd->mii_reg, result); 1647 1648 } 1649 cmd++; 1650 } 1651 } 1652 1653 /* Relocate the function pointers in the phy cmd lists */ 1654 static void relocate_cmds(void) 1655 { 1656 struct phy_cmd **cmdlistptr; 1657 struct phy_cmd *cmd; 1658 int i, j, k; 1659 1660 for (i = 0; phy_info[i]; i++) { 1661 /* First thing's first: relocate the pointers to the 1662 * PHY command structures (the structs were done) */ 1663 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1664 + gd->reloc_off); 1665 phy_info[i]->name += gd->reloc_off; 1666 phy_info[i]->config = 1667 (struct phy_cmd *)((uint) phy_info[i]->config 1668 + gd->reloc_off); 1669 phy_info[i]->startup = 1670 (struct phy_cmd *)((uint) phy_info[i]->startup 1671 + gd->reloc_off); 1672 phy_info[i]->shutdown = 1673 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1674 + gd->reloc_off); 1675 1676 cmdlistptr = &phy_info[i]->config; 1677 j = 0; 1678 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1679 k = 0; 1680 for (cmd = *cmdlistptr; 1681 cmd->mii_reg != miim_end; 1682 cmd++) { 1683 /* Only relocate non-NULL pointers */ 1684 if (cmd->funct) 1685 cmd->funct += gd->reloc_off; 1686 1687 k++; 1688 } 1689 j++; 1690 } 1691 } 1692 1693 relocated = 1; 1694 } 1695 1696 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1697 && !defined(BITBANGMII) 1698 1699 /* 1700 * Read a MII PHY register. 1701 * 1702 * Returns: 1703 * 0 on success 1704 */ 1705 static int tsec_miiphy_read(char *devname, unsigned char addr, 1706 unsigned char reg, unsigned short *value) 1707 { 1708 unsigned short ret; 1709 struct tsec_private *priv = privlist[0]; 1710 1711 if (NULL == priv) { 1712 printf("Can't read PHY at address %d\n", addr); 1713 return -1; 1714 } 1715 1716 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1717 *value = ret; 1718 1719 return 0; 1720 } 1721 1722 /* 1723 * Write a MII PHY register. 1724 * 1725 * Returns: 1726 * 0 on success 1727 */ 1728 static int tsec_miiphy_write(char *devname, unsigned char addr, 1729 unsigned char reg, unsigned short value) 1730 { 1731 struct tsec_private *priv = privlist[0]; 1732 1733 if (NULL == priv) { 1734 printf("Can't write PHY at address %d\n", addr); 1735 return -1; 1736 } 1737 1738 write_any_phy_reg(priv, addr, reg, value); 1739 1740 return 0; 1741 } 1742 1743 #endif 1744 1745 #ifdef CONFIG_MCAST_TFTP 1746 1747 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1748 1749 /* Set the appropriate hash bit for the given addr */ 1750 1751 /* The algorithm works like so: 1752 * 1) Take the Destination Address (ie the multicast address), and 1753 * do a CRC on it (little endian), and reverse the bits of the 1754 * result. 1755 * 2) Use the 8 most significant bits as a hash into a 256-entry 1756 * table. The table is controlled through 8 32-bit registers: 1757 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1758 * gaddr7. This means that the 3 most significant bits in the 1759 * hash index which gaddr register to use, and the 5 other bits 1760 * indicate which bit (assuming an IBM numbering scheme, which 1761 * for PowerPC (tm) is usually the case) in the tregister holds 1762 * the entry. */ 1763 static int 1764 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1765 { 1766 struct tsec_private *priv = privlist[1]; 1767 volatile tsec_t *regs = priv->regs; 1768 volatile u32 *reg_array, value; 1769 u8 result, whichbit, whichreg; 1770 1771 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1772 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1773 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1774 value = (1 << (31-whichbit)); 1775 1776 reg_array = &(regs->hash.gaddr0); 1777 1778 if (set) { 1779 reg_array[whichreg] |= value; 1780 } else { 1781 reg_array[whichreg] &= ~value; 1782 } 1783 return 0; 1784 } 1785 #endif /* Multicast TFTP ? */ 1786