treewide: replace #include <asm/errno.h> with <linux/errno.h>

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)

Replace

treewide: replace #include <asm/errno.h> with <linux/errno.h>

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge branch 'master' of git://git.denx.de/u-boot-net

net: mii: Fix changes made by spatch

Some of the changes were a bit too complex.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

net: mii: Use spatch to update miiphy_register

Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng

net: mii: Use spatch to update miiphy_register

Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Fix GCC format-security errors and convert sprintfs.

With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprint

Fix GCC format-security errors and convert sprintfs.

With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

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net: lpc32xx: fix ignored MDIO busy wait status on read

The change fixes PHY write operation, which incorrectly waits for
released busy state before issuing a write operation, this breaks
sequential

net: lpc32xx: fix ignored MDIO busy wait status on read

The change fixes PHY write operation, which incorrectly waits for
released busy state before issuing a write operation, this breaks
sequential write/read operation logic, because read operation
starts immediately on request and it completes, when busy state is
gone.

Instead of adding the second preceding busy state check to read
function, do busy state release check after issuing a write operation,
this method of operation is also recommended by the LPC32xx User's
Manual, see MII Mgmt Indicators Register notes:

For PHY Write if scan is not used:
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND

Reported-by: Alexandre Messier <amessier@tycoint.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Alexandre Messier <amessier@tycoint.com>

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net: lpc32xx: eth buffers base config

Add support to specify the Ethernet buffer base address;
if none are supply by the board, the default value is use (from existing code).

Signed-off-by: Sylvain

net: lpc32xx: eth buffers base config

Add support to specify the Ethernet buffer base address;
if none are supply by the board, the default value is use (from existing code).

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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Merge branch 'master' of git://git.denx.de/u-boot-net

net: lpc32xx: add RMII phy mode support

LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.

It's worth to mention that the kernel and legacy

net: lpc32xx: add RMII phy mode support

LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.

It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.

Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>

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net: lpc32xx: improve MAC configuration on reset and initialization

This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before t

net: lpc32xx: improve MAC configuration on reset and initialization

This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.

Without the change auto negotiation on boot quite often is not
completed in reasonable time:

Waiting for PHY auto negotiation to complete......... TIMEOUT !

Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

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net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id

The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32x

net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id

The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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net: lpc32xx: correct command register reset value

According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:

Bit Symbol
2 - Unused
3 RegReset

net: lpc32xx: correct command register reset value

According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:

Bit Symbol
2 - Unused
3 RegReset
4 TxReset
5 RxReset

Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

net: cosmetic: Fix var naming net <-> eth drivers

Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the te

net: cosmetic: Fix var naming net <-> eth drivers

Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

lpc32xx: add Ethernet support

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>