1 /* 2 * LPC32xx Ethernet MAC interface driver 3 * 4 * (C) Copyright 2014 DENX Software Engineering GmbH 5 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <malloc.h> 13 #include <miiphy.h> 14 #include <asm/io.h> 15 #include <asm/errno.h> 16 #include <asm/types.h> 17 #include <asm/system.h> 18 #include <asm/byteorder.h> 19 #include <asm/arch/cpu.h> 20 #include <asm/arch/config.h> 21 22 /* 23 * Notes: 24 * 25 * 1. Unless specified otherwise, all references to tables or paragraphs 26 * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". 27 * 28 * 2. Only bitfield masks/values which are actually used by the driver 29 * are defined. 30 */ 31 32 /* a single RX descriptor. The controller has an array of these */ 33 struct lpc32xx_eth_rxdesc { 34 u32 packet; /* Receive packet pointer */ 35 u32 control; /* Descriptor command status */ 36 }; 37 38 #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) 39 40 /* RX control bitfields/masks (see Table 330) */ 41 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF 42 #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 43 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 44 45 /* a single RX status. The controller has an array of these */ 46 struct lpc32xx_eth_rxstat { 47 u32 statusinfo; /* Transmit Descriptor status */ 48 u32 statushashcrc; /* Transmit Descriptor CRCs */ 49 }; 50 51 #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) 52 53 /* RX statusinfo bitfields/masks (see Table 333) */ 54 #define RX_STAT_RXSIZE 0x000007FF 55 /* Helper: OR of all errors except RANGE */ 56 #define RX_STAT_ERRORS 0x1B800000 57 58 /* a single TX descriptor. The controller has an array of these */ 59 struct lpc32xx_eth_txdesc { 60 u32 packet; /* Transmit packet pointer */ 61 u32 control; /* Descriptor control */ 62 }; 63 64 #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) 65 66 /* TX control bitfields/masks (see Table 335) */ 67 #define TX_CTRL_TXSIZE 0x000007FF 68 #define TX_CTRL_LAST 0x40000000 69 70 /* a single TX status. The controller has an array of these */ 71 struct lpc32xx_eth_txstat { 72 u32 statusinfo; /* Transmit Descriptor status */ 73 }; 74 75 #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) 76 77 /* Ethernet MAC interface registers (see Table 283) */ 78 struct lpc32xx_eth_registers { 79 /* MAC registers - 0x3106_0000 to 0x3106_01FC */ 80 u32 mac1; /* MAC configuration register 1 */ 81 u32 mac2; /* MAC configuration register 2 */ 82 u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ 83 u32 ipgr; /* Non-back-to-back IPG register */ 84 u32 clrt; /* Collision Window / Retry register */ 85 u32 maxf; /* Maximum Frame register */ 86 u32 supp; /* Phy Support register */ 87 u32 test; 88 u32 mcfg; /* MII management configuration reg. */ 89 u32 mcmd; /* MII management command register */ 90 u32 madr; /* MII management address register */ 91 u32 mwtd; /* MII management wite data register */ 92 u32 mrdd; /* MII management read data register */ 93 u32 mind; /* MII management indicators register */ 94 u32 reserved1[2]; 95 u32 sa0; /* Station address register 0 */ 96 u32 sa1; /* Station address register 1 */ 97 u32 sa2; /* Station address register 2 */ 98 u32 reserved2[45]; 99 /* Control registers */ 100 u32 command; 101 u32 status; 102 u32 rxdescriptor; 103 u32 rxstatus; 104 u32 rxdescriptornumber; /* actually, number MINUS ONE */ 105 u32 rxproduceindex; /* head of rx desc fifo */ 106 u32 rxconsumeindex; /* tail of rx desc fifo */ 107 u32 txdescriptor; 108 u32 txstatus; 109 u32 txdescriptornumber; /* actually, number MINUS ONE */ 110 u32 txproduceindex; /* head of rx desc fifo */ 111 u32 txconsumeindex; /* tail of rx desc fifo */ 112 u32 reserved3[10]; 113 u32 tsv0; /* Transmit status vector register 0 */ 114 u32 tsv1; /* Transmit status vector register 1 */ 115 u32 rsv; /* Receive status vector register */ 116 u32 reserved4[3]; 117 u32 flowcontrolcounter; 118 u32 flowcontrolstatus; 119 u32 reserved5[34]; 120 /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ 121 u32 rxfilterctrl; 122 u32 rxfilterwolstatus; 123 u32 rxfilterwolclear; 124 u32 reserved6; 125 u32 hashfilterl; 126 u32 hashfilterh; 127 u32 reserved7[882]; 128 /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ 129 u32 intstatus; /* Interrupt status register */ 130 u32 intenable; 131 u32 intclear; 132 u32 intset; 133 u32 reserved8; 134 u32 powerdown; 135 u32 reserved9; 136 }; 137 138 /* MAC1 register bitfields/masks and offsets (see Table 283) */ 139 #define MAC1_RECV_ENABLE 0x00000001 140 #define MAC1_PASS_ALL_RX_FRAMES 0x00000002 141 #define MAC1_SOFT_RESET 0x00008000 142 /* Helper: general reset */ 143 #define MAC1_RESETS 0x0000CF00 144 145 /* MAC2 register bitfields/masks and offsets (see Table 284) */ 146 #define MAC2_FULL_DUPLEX 0x00000001 147 #define MAC2_CRC_ENABLE 0x00000010 148 #define MAC2_PAD_CRC_ENABLE 0x00000020 149 150 /* SUPP register bitfields/masks and offsets (see Table 290) */ 151 #define SUPP_SPEED 0x00000100 152 153 /* MCFG register bitfields/masks and offsets (see Table 292) */ 154 #define MCFG_RESET_MII_MGMT 0x00008000 155 /* divide clock by 28 (see Table 293) */ 156 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C 157 158 /* MADR register bitfields/masks and offsets (see Table 295) */ 159 #define MADR_REG_MASK 0x0000001F 160 #define MADR_PHY_MASK 0x00001F00 161 #define MADR_REG_OFFSET 0 162 #define MADR_PHY_OFFSET 8 163 164 /* MIND register bitfields/masks (see Table 298) */ 165 #define MIND_BUSY 0x00000001 166 167 /* COMMAND register bitfields/masks and offsets (see Table 283) */ 168 #define COMMAND_RXENABLE 0x00000001 169 #define COMMAND_TXENABLE 0x00000002 170 #define COMMAND_PASSRUNTFRAME 0x00000040 171 #define COMMAND_RMII 0x00000200 172 #define COMMAND_FULL_DUPLEX 0x00000400 173 /* Helper: general reset */ 174 #define COMMAND_RESETS 0x00000038 175 176 /* STATUS register bitfields/masks and offsets (see Table 283) */ 177 #define STATUS_RXSTATUS 0x00000001 178 #define STATUS_TXSTATUS 0x00000002 179 180 /* RXFILTERCTRL register bitfields/masks (see Table 319) */ 181 #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 182 #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 183 184 /* Buffers and descriptors */ 185 186 #define ATTRS(n) __aligned(n) 187 188 #define TX_BUF_COUNT 4 189 #define RX_BUF_COUNT 4 190 191 struct lpc32xx_eth_buffers { 192 ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; 193 ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; 194 ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; 195 ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; 196 ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; 197 ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; 198 }; 199 200 /* port device data struct */ 201 struct lpc32xx_eth_device { 202 struct eth_device dev; 203 struct lpc32xx_eth_registers *regs; 204 struct lpc32xx_eth_buffers *bufs; 205 bool phy_rmii; 206 }; 207 208 #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) 209 210 /* generic macros */ 211 #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) 212 213 /* timeout for MII polling */ 214 #define MII_TIMEOUT 10000000 215 216 /* limits for PHY and register addresses */ 217 #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) 218 219 #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) 220 221 DECLARE_GLOBAL_DATA_PTR; 222 223 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 224 /* 225 * mii_reg_read - miiphy_read callback function. 226 * 227 * Returns 16bit phy register value, or 0xffff on error 228 */ 229 static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) 230 { 231 struct eth_device *dev = eth_get_dev_by_name(devname); 232 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); 233 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; 234 u32 mind_reg; 235 u32 timeout; 236 237 /* check parameters */ 238 if (phy_adr > MII_MAX_PHY) { 239 printf("%s:%u: Invalid PHY address %d\n", 240 __func__, __LINE__, phy_adr); 241 return -EFAULT; 242 } 243 if (reg_ofs > MII_MAX_REG) { 244 printf("%s:%u: Invalid register offset %d\n", 245 __func__, __LINE__, reg_ofs); 246 return -EFAULT; 247 } 248 249 /* write the phy and reg addressse into the MII address reg */ 250 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), 251 ®s->madr); 252 253 /* write 1 to the MII command register to cause a read */ 254 writel(1, ®s->mcmd); 255 256 /* wait till the MII is not busy */ 257 timeout = MII_TIMEOUT; 258 do { 259 /* read MII indicators register */ 260 mind_reg = readl(®s->mind); 261 if (--timeout == 0) 262 break; 263 } while (mind_reg & MIND_BUSY); 264 265 /* write 0 to the MII command register to finish the read */ 266 writel(0, ®s->mcmd); 267 268 if (timeout == 0) { 269 printf("%s:%u: MII busy timeout\n", __func__, __LINE__); 270 return -EFAULT; 271 } 272 273 *data = (u16) readl(®s->mrdd); 274 275 debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, 276 reg_ofs, *data); 277 278 return 0; 279 } 280 281 /* 282 * mii_reg_write - imiiphy_write callback function. 283 * 284 * Returns 0 if write succeed, -EINVAL on bad parameters 285 * -ETIME on timeout 286 */ 287 static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) 288 { 289 struct eth_device *dev = eth_get_dev_by_name(devname); 290 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); 291 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; 292 u32 mind_reg; 293 u32 timeout; 294 295 /* check parameters */ 296 if (phy_adr > MII_MAX_PHY) { 297 printf("%s:%u: Invalid PHY address %d\n", 298 __func__, __LINE__, phy_adr); 299 return -EFAULT; 300 } 301 if (reg_ofs > MII_MAX_REG) { 302 printf("%s:%u: Invalid register offset %d\n", 303 __func__, __LINE__, reg_ofs); 304 return -EFAULT; 305 } 306 307 /* wait till the MII is not busy */ 308 timeout = MII_TIMEOUT; 309 do { 310 /* read MII indicators register */ 311 mind_reg = readl(®s->mind); 312 if (--timeout == 0) 313 break; 314 } while (mind_reg & MIND_BUSY); 315 316 if (timeout == 0) { 317 printf("%s:%u: MII busy timeout\n", __func__, 318 __LINE__); 319 return -EFAULT; 320 } 321 322 /* write the phy and reg addressse into the MII address reg */ 323 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), 324 ®s->madr); 325 326 /* write data to the MII write register */ 327 writel(data, ®s->mwtd); 328 329 /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, 330 reg_ofs, data);*/ 331 332 return 0; 333 } 334 #endif 335 336 #if defined(CONFIG_PHYLIB) 337 int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, 338 int reg_addr) 339 { 340 u16 data; 341 int ret; 342 ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data); 343 if (ret) 344 return ret; 345 return data; 346 } 347 348 int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, 349 int reg_addr, u16 data) 350 { 351 return mii_reg_write(bus->name, phy_addr, reg_addr, data); 352 } 353 #endif 354 355 /* 356 * Locate buffers in SRAM at 0x00001000 to avoid cache issues and 357 * maximize throughput. 358 */ 359 360 #define LPC32XX_ETH_BUFS 0x00001000 361 362 static struct lpc32xx_eth_device lpc32xx_eth = { 363 .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, 364 .bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS, 365 #if defined(CONFIG_RMII) 366 .phy_rmii = true, 367 #endif 368 }; 369 370 #define TX_TIMEOUT 10000 371 372 static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) 373 { 374 struct lpc32xx_eth_device *lpc32xx_eth_device = 375 container_of(dev, struct lpc32xx_eth_device, dev); 376 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; 377 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; 378 int timeout, tx_index; 379 380 /* time out if transmit descriptor array remains full too long */ 381 timeout = TX_TIMEOUT; 382 while ((readl(®s->status) & STATUS_TXSTATUS) && 383 (readl(®s->txconsumeindex) 384 == readl(®s->txproduceindex))) { 385 if (timeout-- == 0) 386 return -1; 387 } 388 389 /* determine next transmit packet index to use */ 390 tx_index = readl(®s->txproduceindex); 391 392 /* set up transmit packet */ 393 writel((u32)dataptr, &bufs->tx_desc[tx_index].packet); 394 writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), 395 &bufs->tx_desc[tx_index].control); 396 writel(0, &bufs->tx_stat[tx_index].statusinfo); 397 398 /* pass transmit packet to DMA engine */ 399 tx_index = (tx_index + 1) % TX_BUF_COUNT; 400 writel(tx_index, ®s->txproduceindex); 401 402 /* transmission succeeded */ 403 return 0; 404 } 405 406 #define RX_TIMEOUT 1000000 407 408 static int lpc32xx_eth_recv(struct eth_device *dev) 409 { 410 struct lpc32xx_eth_device *lpc32xx_eth_device = 411 container_of(dev, struct lpc32xx_eth_device, dev); 412 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; 413 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; 414 int timeout, rx_index; 415 416 /* time out if receive descriptor array remains empty too long */ 417 timeout = RX_TIMEOUT; 418 while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { 419 if (timeout-- == 0) 420 return -1; 421 } 422 423 /* determine next receive packet index to use */ 424 rx_index = readl(®s->rxconsumeindex); 425 426 /* if data was valid, pass it on */ 427 if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) { 428 net_process_received_packet( 429 &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]), 430 (bufs->rx_stat[rx_index].statusinfo 431 & RX_STAT_RXSIZE) + 1); 432 } 433 434 /* pass receive slot back to DMA engine */ 435 rx_index = (rx_index + 1) % RX_BUF_COUNT; 436 writel(rx_index, ®s->rxconsumeindex); 437 438 /* reception successful */ 439 return 0; 440 } 441 442 static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) 443 { 444 struct lpc32xx_eth_device *lpc32xx_eth_device = 445 container_of(dev, struct lpc32xx_eth_device, dev); 446 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; 447 448 /* Save station address */ 449 writel((unsigned long) (dev->enetaddr[0] | 450 (dev->enetaddr[1] << 8)), ®s->sa2); 451 writel((unsigned long) (dev->enetaddr[2] | 452 (dev->enetaddr[3] << 8)), ®s->sa1); 453 writel((unsigned long) (dev->enetaddr[4] | 454 (dev->enetaddr[5] << 8)), ®s->sa0); 455 456 return 0; 457 } 458 459 static int lpc32xx_eth_init(struct eth_device *dev) 460 { 461 struct lpc32xx_eth_device *lpc32xx_eth_device = 462 container_of(dev, struct lpc32xx_eth_device, dev); 463 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; 464 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; 465 int index; 466 467 /* Initial MAC initialization */ 468 writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); 469 writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); 470 writel(PKTSIZE_ALIGN, ®s->maxf); 471 472 /* Retries: 15 (0xF). Collision window: 57 (0x37). */ 473 writel(0x370F, ®s->clrt); 474 475 /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ 476 writel(0x0012, ®s->ipgr); 477 478 /* pass runt (smaller than 64 bytes) frames */ 479 if (lpc32xx_eth_device->phy_rmii) 480 writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command); 481 else 482 writel(COMMAND_PASSRUNTFRAME, ®s->command); 483 484 /* Configure Full/Half Duplex mode */ 485 if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { 486 setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); 487 setbits_le32(®s->command, COMMAND_FULL_DUPLEX); 488 writel(0x15, ®s->ipgt); 489 } else { 490 writel(0x12, ®s->ipgt); 491 } 492 493 /* Configure 100MBit/10MBit mode */ 494 if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) 495 writel(SUPP_SPEED, ®s->supp); 496 else 497 writel(0, ®s->supp); 498 499 /* Save station address */ 500 writel((unsigned long) (dev->enetaddr[0] | 501 (dev->enetaddr[1] << 8)), ®s->sa2); 502 writel((unsigned long) (dev->enetaddr[2] | 503 (dev->enetaddr[3] << 8)), ®s->sa1); 504 writel((unsigned long) (dev->enetaddr[4] | 505 (dev->enetaddr[5] << 8)), ®s->sa0); 506 507 /* set up transmit buffers */ 508 for (index = 0; index < TX_BUF_COUNT; index++) { 509 bufs->tx_desc[index].control = 0; 510 bufs->tx_stat[index].statusinfo = 0; 511 } 512 writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); 513 writel((u32)(&bufs->tx_stat), ®s->txstatus); 514 writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); 515 516 /* set up receive buffers */ 517 for (index = 0; index < RX_BUF_COUNT; index++) { 518 bufs->rx_desc[index].packet = 519 (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); 520 bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; 521 bufs->rx_stat[index].statusinfo = 0; 522 bufs->rx_stat[index].statushashcrc = 0; 523 } 524 writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); 525 writel((u32)(&bufs->rx_stat), ®s->rxstatus); 526 writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); 527 528 /* Enable broadcast and matching address packets */ 529 writel(RXFILTERCTRL_ACCEPTBROADCAST | 530 RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); 531 532 /* Clear and disable interrupts */ 533 writel(0xFFFF, ®s->intclear); 534 writel(0, ®s->intenable); 535 536 /* Enable receive and transmit mode of MAC ethernet core */ 537 setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); 538 setbits_le32(®s->mac1, MAC1_RECV_ENABLE); 539 540 /* 541 * Perform a 'dummy' first send to work around Ethernet.1 542 * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). 543 * Use zeroed "index" variable as the dummy. 544 */ 545 546 index = 0; 547 lpc32xx_eth_send(dev, &index, 4); 548 549 return 0; 550 } 551 552 static int lpc32xx_eth_halt(struct eth_device *dev) 553 { 554 struct lpc32xx_eth_device *lpc32xx_eth_device = 555 container_of(dev, struct lpc32xx_eth_device, dev); 556 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; 557 558 /* Reset all MAC logic */ 559 writel(MAC1_RESETS, ®s->mac1); 560 writel(COMMAND_RESETS, ®s->command); 561 /* Let reset condition settle */ 562 udelay(2000); 563 564 return 0; 565 } 566 567 #if defined(CONFIG_PHYLIB) 568 int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) 569 { 570 struct lpc32xx_eth_device *lpc32xx_eth_device = 571 container_of(dev, struct lpc32xx_eth_device, dev); 572 struct mii_dev *bus; 573 struct phy_device *phydev; 574 int ret; 575 576 bus = mdio_alloc(); 577 if (!bus) { 578 printf("mdio_alloc failed\n"); 579 return -ENOMEM; 580 } 581 bus->read = lpc32xx_eth_phy_read; 582 bus->write = lpc32xx_eth_phy_write; 583 sprintf(bus->name, dev->name); 584 585 ret = mdio_register(bus); 586 if (ret) { 587 printf("mdio_register failed\n"); 588 free(bus); 589 return -ENOMEM; 590 } 591 592 if (lpc32xx_eth_device->phy_rmii) 593 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII); 594 else 595 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); 596 597 if (!phydev) { 598 printf("phy_connect failed\n"); 599 return -ENODEV; 600 } 601 602 phy_config(phydev); 603 phy_startup(phydev); 604 605 return 0; 606 } 607 #endif 608 609 int lpc32xx_eth_initialize(bd_t *bis) 610 { 611 struct eth_device *dev = &lpc32xx_eth.dev; 612 struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; 613 614 /* 615 * Set RMII management clock rate. With HCLK at 104 MHz and 616 * a divider of 28, this will be 3.72 MHz. 617 */ 618 writel(MCFG_RESET_MII_MGMT, ®s->mcfg); 619 writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); 620 621 /* Reset all MAC logic */ 622 writel(MAC1_RESETS, ®s->mac1); 623 writel(COMMAND_RESETS, ®s->command); 624 625 /* wait 10 ms for the whole I/F to reset */ 626 udelay(10000); 627 628 /* must be less than sizeof(dev->name) */ 629 strcpy(dev->name, "eth0"); 630 631 dev->init = (void *)lpc32xx_eth_init; 632 dev->halt = (void *)lpc32xx_eth_halt; 633 dev->send = (void *)lpc32xx_eth_send; 634 dev->recv = (void *)lpc32xx_eth_recv; 635 dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; 636 637 /* Release SOFT reset to let MII talk to PHY */ 638 clrbits_le32(®s->mac1, MAC1_SOFT_RESET); 639 640 /* register driver before talking to phy */ 641 eth_register(dev); 642 643 #if defined(CONFIG_PHYLIB) 644 lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); 645 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 646 miiphy_register(dev->name, mii_reg_read, mii_reg_write); 647 #endif 648 649 return 0; 650 } 651