1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 #include <linux/sizes.h> 20 #include <dma.h> 21 22 #include "sf_internal.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static void spi_flash_addr(u32 addr, u8 *cmd) 27 { 28 /* cmd[0] is actual command */ 29 cmd[1] = addr >> 16; 30 cmd[2] = addr >> 8; 31 cmd[3] = addr >> 0; 32 } 33 34 static int read_sr(struct spi_flash *flash, u8 *rs) 35 { 36 int ret; 37 u8 cmd; 38 39 cmd = CMD_READ_STATUS; 40 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 41 if (ret < 0) { 42 debug("SF: fail to read status register\n"); 43 return ret; 44 } 45 46 return 0; 47 } 48 49 static int read_fsr(struct spi_flash *flash, u8 *fsr) 50 { 51 int ret; 52 const u8 cmd = CMD_FLAG_STATUS; 53 54 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 55 if (ret < 0) { 56 debug("SF: fail to read flag status register\n"); 57 return ret; 58 } 59 60 return 0; 61 } 62 63 static int write_sr(struct spi_flash *flash, u8 ws) 64 { 65 u8 cmd; 66 int ret; 67 68 cmd = CMD_WRITE_STATUS; 69 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 70 if (ret < 0) { 71 debug("SF: fail to write status register\n"); 72 return ret; 73 } 74 75 return 0; 76 } 77 78 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 79 static int read_cr(struct spi_flash *flash, u8 *rc) 80 { 81 int ret; 82 u8 cmd; 83 84 cmd = CMD_READ_CONFIG; 85 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 86 if (ret < 0) { 87 debug("SF: fail to read config register\n"); 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int write_cr(struct spi_flash *flash, u8 wc) 95 { 96 u8 data[2]; 97 u8 cmd; 98 int ret; 99 100 ret = read_sr(flash, &data[0]); 101 if (ret < 0) 102 return ret; 103 104 cmd = CMD_WRITE_STATUS; 105 data[1] = wc; 106 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 107 if (ret) { 108 debug("SF: fail to write config register\n"); 109 return ret; 110 } 111 112 return 0; 113 } 114 #endif 115 116 #ifdef CONFIG_SPI_FLASH_BAR 117 /* 118 * This "clean_bar" is necessary in a situation when one was accessing 119 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 120 * 121 * After it the BA24 bit shall be cleared to allow access to correct 122 * memory region after SW reset (by calling "reset" command). 123 * 124 * Otherwise, the BA24 bit may be left set and then after reset, the 125 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 126 */ 127 static int clean_bar(struct spi_flash *flash) 128 { 129 u8 cmd, bank_sel = 0; 130 131 if (flash->bank_curr == 0) 132 return 0; 133 cmd = flash->bank_write_cmd; 134 flash->bank_curr = 0; 135 136 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 137 } 138 139 static int write_bar(struct spi_flash *flash, u32 offset) 140 { 141 u8 cmd, bank_sel; 142 int ret; 143 144 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 145 if (bank_sel == flash->bank_curr) 146 goto bar_end; 147 148 cmd = flash->bank_write_cmd; 149 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 150 if (ret < 0) { 151 debug("SF: fail to write bank register\n"); 152 return ret; 153 } 154 155 bar_end: 156 flash->bank_curr = bank_sel; 157 return flash->bank_curr; 158 } 159 160 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info) 161 { 162 u8 curr_bank = 0; 163 int ret; 164 165 if (flash->size <= SPI_FLASH_16MB_BOUN) 166 goto bar_end; 167 168 switch (JEDEC_MFR(info)) { 169 case SPI_FLASH_CFI_MFR_SPANSION: 170 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 171 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 172 break; 173 default: 174 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 175 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 176 } 177 178 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 179 &curr_bank, 1); 180 if (ret) { 181 debug("SF: fail to read bank addr register\n"); 182 return ret; 183 } 184 185 bar_end: 186 flash->bank_curr = curr_bank; 187 return 0; 188 } 189 #endif 190 191 #ifdef CONFIG_SF_DUAL_FLASH 192 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 193 { 194 switch (flash->dual_flash) { 195 case SF_DUAL_STACKED_FLASH: 196 if (*addr >= (flash->size >> 1)) { 197 *addr -= flash->size >> 1; 198 flash->flags |= SNOR_F_USE_UPAGE; 199 } else { 200 flash->flags &= ~SNOR_F_USE_UPAGE; 201 } 202 break; 203 case SF_DUAL_PARALLEL_FLASH: 204 *addr >>= flash->shift; 205 break; 206 default: 207 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 208 break; 209 } 210 } 211 #endif 212 213 static int spi_flash_sr_ready(struct spi_flash *flash) 214 { 215 u8 sr; 216 int ret; 217 218 ret = read_sr(flash, &sr); 219 if (ret < 0) 220 return ret; 221 222 return !(sr & STATUS_WIP); 223 } 224 225 static int spi_flash_fsr_ready(struct spi_flash *flash) 226 { 227 u8 fsr; 228 int ret; 229 230 ret = read_fsr(flash, &fsr); 231 if (ret < 0) 232 return ret; 233 234 return fsr & STATUS_PEC; 235 } 236 237 static int spi_flash_ready(struct spi_flash *flash) 238 { 239 int sr, fsr; 240 241 sr = spi_flash_sr_ready(flash); 242 if (sr < 0) 243 return sr; 244 245 fsr = 1; 246 if (flash->flags & SNOR_F_USE_FSR) { 247 fsr = spi_flash_fsr_ready(flash); 248 if (fsr < 0) 249 return fsr; 250 } 251 252 return sr && fsr; 253 } 254 255 static int spi_flash_wait_till_ready(struct spi_flash *flash, 256 unsigned long timeout) 257 { 258 unsigned long timebase; 259 int ret; 260 261 timebase = get_timer(0); 262 263 while (get_timer(timebase) < timeout) { 264 ret = spi_flash_ready(flash); 265 if (ret < 0) 266 return ret; 267 if (ret) 268 return 0; 269 } 270 271 printf("SF: Timeout!\n"); 272 273 return -ETIMEDOUT; 274 } 275 276 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 277 size_t cmd_len, const void *buf, size_t buf_len) 278 { 279 struct spi_slave *spi = flash->spi; 280 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 281 int ret; 282 283 if (buf == NULL) 284 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 285 286 ret = spi_claim_bus(spi); 287 if (ret) { 288 debug("SF: unable to claim SPI bus\n"); 289 return ret; 290 } 291 292 ret = spi_flash_cmd_write_enable(flash); 293 if (ret < 0) { 294 debug("SF: enabling write failed\n"); 295 return ret; 296 } 297 298 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 299 if (ret < 0) { 300 debug("SF: write cmd failed\n"); 301 return ret; 302 } 303 304 ret = spi_flash_wait_till_ready(flash, timeout); 305 if (ret < 0) { 306 debug("SF: write %s timed out\n", 307 timeout == SPI_FLASH_PROG_TIMEOUT ? 308 "program" : "page erase"); 309 return ret; 310 } 311 312 spi_release_bus(spi); 313 314 return ret; 315 } 316 317 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 318 { 319 u32 erase_size, erase_addr; 320 u8 cmd[SPI_FLASH_CMD_LEN]; 321 int ret = -1; 322 323 erase_size = flash->erase_size; 324 if (offset % erase_size || len % erase_size) { 325 printf("SF: Erase offset/length not multiple of erase size\n"); 326 return -1; 327 } 328 329 if (flash->flash_is_locked) { 330 if (flash->flash_is_locked(flash, offset, len) > 0) { 331 printf("offset 0x%x is protected and cannot be erased\n", 332 offset); 333 return -EINVAL; 334 } 335 } 336 337 cmd[0] = flash->erase_cmd; 338 while (len) { 339 erase_addr = offset; 340 341 #ifdef CONFIG_SF_DUAL_FLASH 342 if (flash->dual_flash > SF_SINGLE_FLASH) 343 spi_flash_dual(flash, &erase_addr); 344 #endif 345 #ifdef CONFIG_SPI_FLASH_BAR 346 ret = write_bar(flash, erase_addr); 347 if (ret < 0) 348 return ret; 349 #endif 350 spi_flash_addr(erase_addr, cmd); 351 352 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 353 cmd[2], cmd[3], erase_addr); 354 355 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 356 if (ret < 0) { 357 debug("SF: erase failed\n"); 358 break; 359 } 360 361 offset += erase_size; 362 len -= erase_size; 363 } 364 365 #ifdef CONFIG_SPI_FLASH_BAR 366 ret = clean_bar(flash); 367 #endif 368 369 return ret; 370 } 371 372 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 373 size_t len, const void *buf) 374 { 375 struct spi_slave *spi = flash->spi; 376 unsigned long byte_addr, page_size; 377 u32 write_addr; 378 size_t chunk_len, actual; 379 u8 cmd[SPI_FLASH_CMD_LEN]; 380 int ret = -1; 381 382 page_size = flash->page_size; 383 384 if (flash->flash_is_locked) { 385 if (flash->flash_is_locked(flash, offset, len) > 0) { 386 printf("offset 0x%x is protected and cannot be written\n", 387 offset); 388 return -EINVAL; 389 } 390 } 391 392 cmd[0] = flash->write_cmd; 393 for (actual = 0; actual < len; actual += chunk_len) { 394 write_addr = offset; 395 396 #ifdef CONFIG_SF_DUAL_FLASH 397 if (flash->dual_flash > SF_SINGLE_FLASH) 398 spi_flash_dual(flash, &write_addr); 399 #endif 400 #ifdef CONFIG_SPI_FLASH_BAR 401 ret = write_bar(flash, write_addr); 402 if (ret < 0) 403 return ret; 404 #endif 405 byte_addr = offset % page_size; 406 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 407 408 if (spi->max_write_size) 409 chunk_len = min(chunk_len, 410 spi->max_write_size - sizeof(cmd)); 411 412 spi_flash_addr(write_addr, cmd); 413 414 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 415 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 416 417 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 418 buf + actual, chunk_len); 419 if (ret < 0) { 420 debug("SF: write failed\n"); 421 break; 422 } 423 424 offset += chunk_len; 425 } 426 427 #ifdef CONFIG_SPI_FLASH_BAR 428 ret = clean_bar(flash); 429 #endif 430 431 return ret; 432 } 433 434 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 435 size_t cmd_len, void *data, size_t data_len) 436 { 437 struct spi_slave *spi = flash->spi; 438 int ret; 439 440 ret = spi_claim_bus(spi); 441 if (ret) { 442 debug("SF: unable to claim SPI bus\n"); 443 return ret; 444 } 445 446 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 447 if (ret < 0) { 448 debug("SF: read cmd failed\n"); 449 return ret; 450 } 451 452 spi_release_bus(spi); 453 454 return ret; 455 } 456 457 /* 458 * TODO: remove the weak after all the other spi_flash_copy_mmap 459 * implementations removed from drivers 460 */ 461 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 462 { 463 #ifdef CONFIG_DMA 464 if (!dma_memcpy(data, offset, len)) 465 return; 466 #endif 467 memcpy(data, offset, len); 468 } 469 470 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 471 size_t len, void *data) 472 { 473 struct spi_slave *spi = flash->spi; 474 u8 cmdsz; 475 u32 remain_len, read_len, read_addr; 476 int bank_sel = 0; 477 int ret = -1; 478 479 /* Handle memory-mapped SPI */ 480 if (flash->memory_map) { 481 ret = spi_claim_bus(spi); 482 if (ret) { 483 debug("SF: unable to claim SPI bus\n"); 484 return ret; 485 } 486 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 487 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 488 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 489 spi_release_bus(spi); 490 return 0; 491 } 492 493 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 494 u8 cmd[cmdsz]; 495 496 cmd[0] = flash->read_cmd; 497 while (len) { 498 read_addr = offset; 499 500 #ifdef CONFIG_SF_DUAL_FLASH 501 if (flash->dual_flash > SF_SINGLE_FLASH) 502 spi_flash_dual(flash, &read_addr); 503 #endif 504 #ifdef CONFIG_SPI_FLASH_BAR 505 ret = write_bar(flash, read_addr); 506 if (ret < 0) 507 return ret; 508 bank_sel = flash->bank_curr; 509 #endif 510 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 511 (bank_sel + 1)) - offset; 512 if (len < remain_len) 513 read_len = len; 514 else 515 read_len = remain_len; 516 517 if (spi->max_read_size) 518 read_len = min(read_len, spi->max_read_size); 519 520 spi_flash_addr(read_addr, cmd); 521 522 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 523 if (ret < 0) { 524 debug("SF: read failed\n"); 525 break; 526 } 527 528 offset += read_len; 529 len -= read_len; 530 data += read_len; 531 } 532 533 #ifdef CONFIG_SPI_FLASH_BAR 534 ret = clean_bar(flash); 535 #endif 536 537 return ret; 538 } 539 540 #ifdef CONFIG_SPI_FLASH_SST 541 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) 542 { 543 switch (ctl) { 544 case SST26_CTL_LOCK: 545 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); 546 break; 547 case SST26_CTL_UNLOCK: 548 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); 549 break; 550 case SST26_CTL_CHECK: 551 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); 552 } 553 554 return false; 555 } 556 557 /* 558 * sst26wf016/sst26wf032/sst26wf064 have next block protection: 559 * 4x - 8 KByte blocks - read & write protection bits - upper addresses 560 * 1x - 32 KByte blocks - write protection bits 561 * rest - 64 KByte blocks - write protection bits 562 * 1x - 32 KByte blocks - write protection bits 563 * 4x - 8 KByte blocks - read & write protection bits - lower addresses 564 * 565 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region 566 * will be treated as single block. 567 */ 568 569 /* 570 * Lock, unlock or check lock status of the flash region of the flash (depending 571 * on the lock_ctl value) 572 */ 573 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl) 574 { 575 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; 576 bool lower_64k = false, upper_64k = false; 577 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; 578 int ret; 579 580 /* Check length and offset for 64k alignment */ 581 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) 582 return -EINVAL; 583 584 if (ofs + len > flash->size) 585 return -EINVAL; 586 587 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ 588 if (flash->size != SZ_2M && 589 flash->size != SZ_4M && 590 flash->size != SZ_8M) 591 return -EINVAL; 592 593 bpr_size = 2 + (flash->size / SZ_64K / 8); 594 595 cmd = SST26_CMD_READ_BPR; 596 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size); 597 if (ret < 0) { 598 printf("SF: fail to read block-protection register\n"); 599 return ret; 600 } 601 602 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE); 603 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); 604 605 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE)); 606 lower_64k = (ofs < SST26_BOUND_REG_SIZE); 607 608 /* Lower bits in block-protection register are about 64k region */ 609 bpr_ptr = lptr_64k / SZ_64K - 1; 610 611 /* Process 64K blocks region */ 612 while (lptr_64k < rptr_64k) { 613 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 614 return EACCES; 615 616 bpr_ptr++; 617 lptr_64k += SZ_64K; 618 } 619 620 /* 32K and 8K region bits in BPR are after 64k region bits */ 621 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; 622 623 /* Process lower 32K block region */ 624 if (lower_64k) 625 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 626 return EACCES; 627 628 bpr_ptr++; 629 630 /* Process upper 32K block region */ 631 if (upper_64k) 632 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 633 return EACCES; 634 635 bpr_ptr++; 636 637 /* Process lower 8K block regions */ 638 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 639 if (lower_64k) 640 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 641 return EACCES; 642 643 /* In 8K area BPR has both read and write protection bits */ 644 bpr_ptr += 2; 645 } 646 647 /* Process upper 8K block regions */ 648 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 649 if (upper_64k) 650 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 651 return EACCES; 652 653 /* In 8K area BPR has both read and write protection bits */ 654 bpr_ptr += 2; 655 } 656 657 /* If we check region status we don't need to write BPR back */ 658 if (ctl == SST26_CTL_CHECK) 659 return 0; 660 661 cmd = SST26_CMD_WRITE_BPR; 662 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size); 663 if (ret < 0) { 664 printf("SF: fail to write block-protection register\n"); 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len) 672 { 673 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK); 674 } 675 676 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len) 677 { 678 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK); 679 } 680 681 /* 682 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, 683 * and negative on errors. 684 */ 685 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 686 { 687 /* 688 * is_locked function is used for check before reading or erasing flash 689 * region, so offset and length might be not 64k allighned, so adjust 690 * them to be 64k allighned as sst26_lock_ctl works only with 64k 691 * allighned regions. 692 */ 693 ofs -= ofs & (SZ_64K - 1); 694 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; 695 696 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK); 697 } 698 699 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 700 { 701 struct spi_slave *spi = flash->spi; 702 int ret; 703 u8 cmd[4] = { 704 CMD_SST_BP, 705 offset >> 16, 706 offset >> 8, 707 offset, 708 }; 709 710 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 711 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 712 713 ret = spi_flash_cmd_write_enable(flash); 714 if (ret) 715 return ret; 716 717 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 718 if (ret) 719 return ret; 720 721 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 722 } 723 724 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 725 const void *buf) 726 { 727 struct spi_slave *spi = flash->spi; 728 size_t actual, cmd_len; 729 int ret; 730 u8 cmd[4]; 731 732 ret = spi_claim_bus(spi); 733 if (ret) { 734 debug("SF: Unable to claim SPI bus\n"); 735 return ret; 736 } 737 738 /* If the data is not word aligned, write out leading single byte */ 739 actual = offset % 2; 740 if (actual) { 741 ret = sst_byte_write(flash, offset, buf); 742 if (ret) 743 goto done; 744 } 745 offset += actual; 746 747 ret = spi_flash_cmd_write_enable(flash); 748 if (ret) 749 goto done; 750 751 cmd_len = 4; 752 cmd[0] = CMD_SST_AAI_WP; 753 cmd[1] = offset >> 16; 754 cmd[2] = offset >> 8; 755 cmd[3] = offset; 756 757 for (; actual < len - 1; actual += 2) { 758 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 759 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 760 cmd[0], offset); 761 762 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 763 buf + actual, 2); 764 if (ret) { 765 debug("SF: sst word program failed\n"); 766 break; 767 } 768 769 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 770 if (ret) 771 break; 772 773 cmd_len = 1; 774 offset += 2; 775 } 776 777 if (!ret) 778 ret = spi_flash_cmd_write_disable(flash); 779 780 /* If there is a single trailing byte, write it out */ 781 if (!ret && actual != len) 782 ret = sst_byte_write(flash, offset, buf + actual); 783 784 done: 785 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 786 ret ? "failure" : "success", len, offset - actual); 787 788 spi_release_bus(spi); 789 return ret; 790 } 791 792 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 793 const void *buf) 794 { 795 struct spi_slave *spi = flash->spi; 796 size_t actual; 797 int ret; 798 799 ret = spi_claim_bus(spi); 800 if (ret) { 801 debug("SF: Unable to claim SPI bus\n"); 802 return ret; 803 } 804 805 for (actual = 0; actual < len; actual++) { 806 ret = sst_byte_write(flash, offset, buf + actual); 807 if (ret) { 808 debug("SF: sst byte program failed\n"); 809 break; 810 } 811 offset++; 812 } 813 814 if (!ret) 815 ret = spi_flash_cmd_write_disable(flash); 816 817 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 818 ret ? "failure" : "success", len, offset - actual); 819 820 spi_release_bus(spi); 821 return ret; 822 } 823 #endif 824 825 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 826 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 827 u64 *len) 828 { 829 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 830 int shift = ffs(mask) - 1; 831 int pow; 832 833 if (!(sr & mask)) { 834 /* No protection */ 835 *ofs = 0; 836 *len = 0; 837 } else { 838 pow = ((sr & mask) ^ mask) >> shift; 839 *len = flash->size >> pow; 840 *ofs = flash->size - *len; 841 } 842 } 843 844 /* 845 * Return 1 if the entire region is locked, 0 otherwise 846 */ 847 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len, 848 u8 sr) 849 { 850 loff_t lock_offs; 851 u64 lock_len; 852 853 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 854 855 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 856 } 857 858 /* 859 * Check if a region of the flash is (completely) locked. See stm_lock() for 860 * more info. 861 * 862 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 863 * negative on errors. 864 */ 865 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 866 { 867 int status; 868 u8 sr; 869 870 status = read_sr(flash, &sr); 871 if (status < 0) 872 return status; 873 874 return stm_is_locked_sr(flash, ofs, len, sr); 875 } 876 877 /* 878 * Lock a region of the flash. Compatible with ST Micro and similar flash. 879 * Supports only the block protection bits BP{0,1,2} in the status register 880 * (SR). Does not support these features found in newer SR bitfields: 881 * - TB: top/bottom protect - only handle TB=0 (top protect) 882 * - SEC: sector/block protect - only handle SEC=0 (block protect) 883 * - CMP: complement protect - only support CMP=0 (range is not complemented) 884 * 885 * Sample table portion for 8MB flash (Winbond w25q64fw): 886 * 887 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 888 * -------------------------------------------------------------------------- 889 * X | X | 0 | 0 | 0 | NONE | NONE 890 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 891 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 892 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 893 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 894 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 895 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 896 * X | X | 1 | 1 | 1 | 8 MB | ALL 897 * 898 * Returns negative on errors, 0 on success. 899 */ 900 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 901 { 902 u8 status_old, status_new; 903 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 904 u8 shift = ffs(mask) - 1, pow, val; 905 int ret; 906 907 ret = read_sr(flash, &status_old); 908 if (ret < 0) 909 return ret; 910 911 /* SPI NOR always locks to the end */ 912 if (ofs + len != flash->size) { 913 /* Does combined region extend to end? */ 914 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 915 status_old)) 916 return -EINVAL; 917 len = flash->size - ofs; 918 } 919 920 /* 921 * Need smallest pow such that: 922 * 923 * 1 / (2^pow) <= (len / size) 924 * 925 * so (assuming power-of-2 size) we do: 926 * 927 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 928 */ 929 pow = ilog2(flash->size) - ilog2(len); 930 val = mask - (pow << shift); 931 if (val & ~mask) 932 return -EINVAL; 933 934 /* Don't "lock" with no region! */ 935 if (!(val & mask)) 936 return -EINVAL; 937 938 status_new = (status_old & ~mask) | val; 939 940 /* Only modify protection if it will not unlock other areas */ 941 if ((status_new & mask) <= (status_old & mask)) 942 return -EINVAL; 943 944 write_sr(flash, status_new); 945 946 return 0; 947 } 948 949 /* 950 * Unlock a region of the flash. See stm_lock() for more info 951 * 952 * Returns negative on errors, 0 on success. 953 */ 954 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 955 { 956 uint8_t status_old, status_new; 957 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 958 u8 shift = ffs(mask) - 1, pow, val; 959 int ret; 960 961 ret = read_sr(flash, &status_old); 962 if (ret < 0) 963 return ret; 964 965 /* Cannot unlock; would unlock larger region than requested */ 966 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 967 status_old)) 968 return -EINVAL; 969 /* 970 * Need largest pow such that: 971 * 972 * 1 / (2^pow) >= (len / size) 973 * 974 * so (assuming power-of-2 size) we do: 975 * 976 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 977 */ 978 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 979 if (ofs + len == flash->size) { 980 val = 0; /* fully unlocked */ 981 } else { 982 val = mask - (pow << shift); 983 /* Some power-of-two sizes are not supported */ 984 if (val & ~mask) 985 return -EINVAL; 986 } 987 988 status_new = (status_old & ~mask) | val; 989 990 /* Only modify protection if it will not lock other areas */ 991 if ((status_new & mask) >= (status_old & mask)) 992 return -EINVAL; 993 994 write_sr(flash, status_new); 995 996 return 0; 997 } 998 #endif 999 1000 1001 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1002 static int macronix_quad_enable(struct spi_flash *flash) 1003 { 1004 u8 qeb_status; 1005 int ret; 1006 1007 ret = read_sr(flash, &qeb_status); 1008 if (ret < 0) 1009 return ret; 1010 1011 if (qeb_status & STATUS_QEB_MXIC) 1012 return 0; 1013 1014 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); 1015 if (ret < 0) 1016 return ret; 1017 1018 /* read SR and check it */ 1019 ret = read_sr(flash, &qeb_status); 1020 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { 1021 printf("SF: Macronix SR Quad bit not clear\n"); 1022 return -EINVAL; 1023 } 1024 1025 return ret; 1026 } 1027 #endif 1028 1029 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1030 static int spansion_quad_enable(struct spi_flash *flash) 1031 { 1032 u8 qeb_status; 1033 int ret; 1034 1035 ret = read_cr(flash, &qeb_status); 1036 if (ret < 0) 1037 return ret; 1038 1039 if (qeb_status & STATUS_QEB_WINSPAN) 1040 return 0; 1041 1042 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); 1043 if (ret < 0) 1044 return ret; 1045 1046 /* read CR and check it */ 1047 ret = read_cr(flash, &qeb_status); 1048 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { 1049 printf("SF: Spansion CR Quad bit not clear\n"); 1050 return -EINVAL; 1051 } 1052 1053 return ret; 1054 } 1055 #endif 1056 1057 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) 1058 { 1059 int tmp; 1060 u8 id[SPI_FLASH_MAX_ID_LEN]; 1061 const struct spi_flash_info *info; 1062 1063 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN); 1064 if (tmp < 0) { 1065 printf("SF: error %d reading JEDEC ID\n", tmp); 1066 return ERR_PTR(tmp); 1067 } 1068 1069 info = spi_flash_ids; 1070 for (; info->name != NULL; info++) { 1071 if (info->id_len) { 1072 if (!memcmp(info->id, id, info->id_len)) 1073 return info; 1074 } 1075 } 1076 1077 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 1078 id[0], id[1], id[2]); 1079 return ERR_PTR(-ENODEV); 1080 } 1081 1082 static int set_quad_mode(struct spi_flash *flash, 1083 const struct spi_flash_info *info) 1084 { 1085 switch (JEDEC_MFR(info)) { 1086 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1087 case SPI_FLASH_CFI_MFR_MACRONIX: 1088 case SPI_FLASH_CIF_MFR_GIGADEVICE: 1089 return macronix_quad_enable(flash); 1090 #endif 1091 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1092 case SPI_FLASH_CFI_MFR_SPANSION: 1093 case SPI_FLASH_CFI_MFR_WINBOND: 1094 return spansion_quad_enable(flash); 1095 #endif 1096 #ifdef CONFIG_SPI_FLASH_STMICRO 1097 case SPI_FLASH_CFI_MFR_STMICRO: 1098 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); 1099 return 0; 1100 #endif 1101 default: 1102 printf("SF: Need set QEB func for %02x flash\n", 1103 JEDEC_MFR(info)); 1104 return -1; 1105 } 1106 } 1107 1108 #if CONFIG_IS_ENABLED(OF_CONTROL) 1109 int spi_flash_decode_fdt(struct spi_flash *flash) 1110 { 1111 #ifdef CONFIG_DM_SPI_FLASH 1112 fdt_addr_t addr; 1113 fdt_size_t size; 1114 1115 addr = dev_read_addr_size(flash->dev, "memory-map", &size); 1116 if (addr == FDT_ADDR_T_NONE) { 1117 debug("%s: Cannot decode address\n", __func__); 1118 return 0; 1119 } 1120 1121 if (flash->size > size) { 1122 debug("%s: Memory map must cover entire device\n", __func__); 1123 return -1; 1124 } 1125 flash->memory_map = map_sysmem(addr, size); 1126 #endif 1127 1128 return 0; 1129 } 1130 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 1131 1132 int spi_flash_scan(struct spi_flash *flash) 1133 { 1134 struct spi_slave *spi = flash->spi; 1135 const struct spi_flash_info *info = NULL; 1136 int ret; 1137 1138 info = spi_flash_read_id(flash); 1139 if (IS_ERR_OR_NULL(info)) 1140 return -ENOENT; 1141 1142 /* 1143 * Flash powers up read-only, so clear BP# bits. 1144 * 1145 * Note on some flash (like Macronix), QE (quad enable) bit is in the 1146 * same status register as BP# bits, and we need preserve its original 1147 * value during a reboot cycle as this is required by some platforms 1148 * (like Intel ICH SPI controller working under descriptor mode). 1149 */ 1150 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || 1151 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) || 1152 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) { 1153 u8 sr = 0; 1154 1155 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { 1156 read_sr(flash, &sr); 1157 sr &= STATUS_QEB_MXIC; 1158 } 1159 write_sr(flash, sr); 1160 } 1161 1162 flash->name = info->name; 1163 flash->memory_map = spi->memory_map; 1164 1165 if (info->flags & SST_WR) 1166 flash->flags |= SNOR_F_SST_WR; 1167 1168 #ifndef CONFIG_DM_SPI_FLASH 1169 flash->write = spi_flash_cmd_write_ops; 1170 #if defined(CONFIG_SPI_FLASH_SST) 1171 if (flash->flags & SNOR_F_SST_WR) { 1172 if (spi->mode & SPI_TX_BYTE) 1173 flash->write = sst_write_bp; 1174 else 1175 flash->write = sst_write_wp; 1176 } 1177 #endif 1178 flash->erase = spi_flash_cmd_erase_ops; 1179 flash->read = spi_flash_cmd_read_ops; 1180 #endif 1181 1182 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 1183 /* NOR protection support for STmicro/Micron chips and similar */ 1184 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO || 1185 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) { 1186 flash->flash_lock = stm_lock; 1187 flash->flash_unlock = stm_unlock; 1188 flash->flash_is_locked = stm_is_locked; 1189 } 1190 #endif 1191 1192 /* sst26wf series block protection implementation differs from other series */ 1193 #if defined(CONFIG_SPI_FLASH_SST) 1194 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) { 1195 flash->flash_lock = sst26_lock; 1196 flash->flash_unlock = sst26_unlock; 1197 flash->flash_is_locked = sst26_is_locked; 1198 } 1199 #endif 1200 1201 /* Compute the flash size */ 1202 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 1203 flash->page_size = info->page_size; 1204 /* 1205 * The Spansion S25FS512S, S25FL032P and S25FL064P have 256b pages, 1206 * yet use the 0x4d00 Extended JEDEC code. The rest of the Spansion 1207 * flashes with the 0x4d00 Extended JEDEC code have 512b pages. 1208 * All of the others have 256b pages. 1209 */ 1210 if (JEDEC_EXT(info) == 0x4d00) { 1211 if ((JEDEC_ID(info) != 0x0215) && 1212 (JEDEC_ID(info) != 0x0216) && 1213 (JEDEC_ID(info) != 0x0220)) 1214 flash->page_size = 512; 1215 } 1216 flash->page_size <<= flash->shift; 1217 flash->sector_size = info->sector_size << flash->shift; 1218 flash->size = flash->sector_size * info->n_sectors << flash->shift; 1219 #ifdef CONFIG_SF_DUAL_FLASH 1220 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1221 flash->size <<= 1; 1222 #endif 1223 1224 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 1225 /* Compute erase sector and command */ 1226 if (info->flags & SECT_4K) { 1227 flash->erase_cmd = CMD_ERASE_4K; 1228 flash->erase_size = 4096 << flash->shift; 1229 } else 1230 #endif 1231 { 1232 flash->erase_cmd = CMD_ERASE_64K; 1233 flash->erase_size = flash->sector_size; 1234 } 1235 1236 /* Now erase size becomes valid sector size */ 1237 flash->sector_size = flash->erase_size; 1238 1239 /* Look for read commands */ 1240 flash->read_cmd = CMD_READ_ARRAY_FAST; 1241 if (spi->mode & SPI_RX_SLOW) 1242 flash->read_cmd = CMD_READ_ARRAY_SLOW; 1243 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) 1244 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; 1245 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) 1246 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; 1247 1248 /* Look for write commands */ 1249 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) 1250 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1251 else 1252 /* Go for default supported write cmd */ 1253 flash->write_cmd = CMD_PAGE_PROGRAM; 1254 1255 /* Set the quad enable bit - only for quad commands */ 1256 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1257 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1258 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1259 ret = set_quad_mode(flash, info); 1260 if (ret) { 1261 debug("SF: Fail to set QEB for %02x\n", 1262 JEDEC_MFR(info)); 1263 return -EINVAL; 1264 } 1265 } 1266 1267 /* Read dummy_byte: dummy byte is determined based on the 1268 * dummy cycles of a particular command. 1269 * Fast commands - dummy_byte = dummy_cycles/8 1270 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1271 * For I/O commands except cmd[0] everything goes on no.of lines 1272 * based on particular command but incase of fast commands except 1273 * data all go on single line irrespective of command. 1274 */ 1275 switch (flash->read_cmd) { 1276 case CMD_READ_QUAD_IO_FAST: 1277 flash->dummy_byte = 2; 1278 break; 1279 case CMD_READ_ARRAY_SLOW: 1280 flash->dummy_byte = 0; 1281 break; 1282 default: 1283 flash->dummy_byte = 1; 1284 } 1285 1286 #ifdef CONFIG_SPI_FLASH_STMICRO 1287 if (info->flags & E_FSR) 1288 flash->flags |= SNOR_F_USE_FSR; 1289 #endif 1290 1291 /* Configure the BAR - discover bank cmds and read current bank */ 1292 #ifdef CONFIG_SPI_FLASH_BAR 1293 ret = read_bar(flash, info); 1294 if (ret < 0) 1295 return ret; 1296 #endif 1297 1298 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1299 ret = spi_flash_decode_fdt(flash); 1300 if (ret) { 1301 debug("SF: FDT decode error\n"); 1302 return -EINVAL; 1303 } 1304 #endif 1305 1306 #ifndef CONFIG_SPL_BUILD 1307 printf("SF: Detected %s with page size ", flash->name); 1308 print_size(flash->page_size, ", erase size "); 1309 print_size(flash->erase_size, ", total "); 1310 print_size(flash->size, ""); 1311 if (flash->memory_map) 1312 printf(", mapped at %p", flash->memory_map); 1313 puts("\n"); 1314 #endif 1315 1316 #ifndef CONFIG_SPI_FLASH_BAR 1317 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1318 (flash->size > SPI_FLASH_16MB_BOUN)) || 1319 ((flash->dual_flash > SF_SINGLE_FLASH) && 1320 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1321 puts("SF: Warning - Only lower 16MiB accessible,"); 1322 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1323 } 1324 #endif 1325 1326 return 0; 1327 } 1328