1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 161 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 162 163 /* We shouldn't wait for data inihibit for stop commands, even 164 though they might use busy signaling */ 165 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 166 mask &= ~SDHCI_DATA_INHIBIT; 167 168 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 169 if (time >= cmd_timeout) { 170 printf("%s: MMC: %d busy ", __func__, mmc_dev); 171 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 172 cmd_timeout += cmd_timeout; 173 printf("timeout increasing to: %u ms.\n", 174 cmd_timeout); 175 } else { 176 puts("timeout.\n"); 177 return -ECOMM; 178 } 179 } 180 time++; 181 udelay(1000); 182 } 183 184 mask = SDHCI_INT_RESPONSE; 185 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 186 flags = SDHCI_CMD_RESP_NONE; 187 else if (cmd->resp_type & MMC_RSP_136) 188 flags = SDHCI_CMD_RESP_LONG; 189 else if (cmd->resp_type & MMC_RSP_BUSY) { 190 flags = SDHCI_CMD_RESP_SHORT_BUSY; 191 if (data) 192 mask |= SDHCI_INT_DATA_END; 193 } else 194 flags = SDHCI_CMD_RESP_SHORT; 195 196 if (cmd->resp_type & MMC_RSP_CRC) 197 flags |= SDHCI_CMD_CRC; 198 if (cmd->resp_type & MMC_RSP_OPCODE) 199 flags |= SDHCI_CMD_INDEX; 200 if (data) 201 flags |= SDHCI_CMD_DATA; 202 203 /* Set Transfer mode regarding to data flag */ 204 if (data != 0) { 205 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 206 mode = SDHCI_TRNS_BLK_CNT_EN; 207 trans_bytes = data->blocks * data->blocksize; 208 if (data->blocks > 1) 209 mode |= SDHCI_TRNS_MULTI; 210 211 if (data->flags == MMC_DATA_READ) 212 mode |= SDHCI_TRNS_READ; 213 214 #ifdef CONFIG_MMC_SDHCI_SDMA 215 if (data->flags == MMC_DATA_READ) 216 start_addr = (unsigned long)data->dest; 217 else 218 start_addr = (unsigned long)data->src; 219 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 220 (start_addr & 0x7) != 0x0) { 221 is_aligned = 0; 222 start_addr = (unsigned long)aligned_buffer; 223 if (data->flags != MMC_DATA_READ) 224 memcpy(aligned_buffer, data->src, trans_bytes); 225 } 226 227 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 228 /* 229 * Always use this bounce-buffer when 230 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 231 */ 232 is_aligned = 0; 233 start_addr = (unsigned long)aligned_buffer; 234 if (data->flags != MMC_DATA_READ) 235 memcpy(aligned_buffer, data->src, trans_bytes); 236 #endif 237 238 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 239 mode |= SDHCI_TRNS_DMA; 240 #endif 241 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 242 data->blocksize), 243 SDHCI_BLOCK_SIZE); 244 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 245 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 246 } else if (cmd->resp_type & MMC_RSP_BUSY) { 247 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 248 } 249 250 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 251 #ifdef CONFIG_MMC_SDHCI_SDMA 252 if (data != 0) { 253 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 254 flush_cache(start_addr, trans_bytes); 255 } 256 #endif 257 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 258 start = get_timer(0); 259 do { 260 stat = sdhci_readl(host, SDHCI_INT_STATUS); 261 if (stat & SDHCI_INT_ERROR) 262 break; 263 264 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 265 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 266 return 0; 267 } else { 268 printf("%s: Timeout for status update!\n", 269 __func__); 270 return -ETIMEDOUT; 271 } 272 } 273 } while ((stat & mask) != mask); 274 275 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 276 sdhci_cmd_done(host, cmd); 277 sdhci_writel(host, mask, SDHCI_INT_STATUS); 278 } else 279 ret = -1; 280 281 if (!ret && data) 282 ret = sdhci_transfer_data(host, data, start_addr); 283 284 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 285 udelay(1000); 286 287 stat = sdhci_readl(host, SDHCI_INT_STATUS); 288 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 289 if (!ret) { 290 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 291 !is_aligned && (data->flags == MMC_DATA_READ)) 292 memcpy(data->dest, aligned_buffer, trans_bytes); 293 return 0; 294 } 295 296 sdhci_reset(host, SDHCI_RESET_CMD); 297 sdhci_reset(host, SDHCI_RESET_DATA); 298 if (stat & SDHCI_INT_TIMEOUT) 299 return -ETIMEDOUT; 300 else 301 return -ECOMM; 302 } 303 304 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 305 { 306 unsigned int div, clk = 0, timeout; 307 308 /* Wait max 20 ms */ 309 timeout = 200; 310 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 311 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 312 if (timeout == 0) { 313 printf("%s: Timeout to wait cmd & data inhibit\n", 314 __func__); 315 return -EBUSY; 316 } 317 318 timeout--; 319 udelay(100); 320 } 321 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 322 323 if (clock == 0) 324 return 0; 325 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 326 /* 327 * Check if the Host Controller supports Programmable Clock 328 * Mode. 329 */ 330 if (host->clk_mul) { 331 for (div = 1; div <= 1024; div++) { 332 if ((host->max_clk / div) <= clock) 333 break; 334 } 335 336 /* 337 * Set Programmable Clock Mode in the Clock 338 * Control register. 339 */ 340 clk = SDHCI_PROG_CLOCK_MODE; 341 div--; 342 } else { 343 /* Version 3.00 divisors must be a multiple of 2. */ 344 if (host->max_clk <= clock) { 345 div = 1; 346 } else { 347 for (div = 2; 348 div < SDHCI_MAX_DIV_SPEC_300; 349 div += 2) { 350 if ((host->max_clk / div) <= clock) 351 break; 352 } 353 } 354 div >>= 1; 355 } 356 } else { 357 /* Version 2.00 divisors must be a power of 2. */ 358 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 359 if ((host->max_clk / div) <= clock) 360 break; 361 } 362 div >>= 1; 363 } 364 if (host->ops && host->ops->set_clock_ext) 365 host->ops->set_clock_ext(host, div); 366 367 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 368 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 369 << SDHCI_DIVIDER_HI_SHIFT; 370 clk |= SDHCI_CLOCK_INT_EN; 371 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 372 373 /* Wait max 20 ms */ 374 timeout = 20; 375 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 376 & SDHCI_CLOCK_INT_STABLE)) { 377 if (timeout == 0) { 378 printf("%s: Internal clock never stabilised.\n", 379 __func__); 380 return -EBUSY; 381 } 382 timeout--; 383 udelay(1000); 384 } 385 clk |= SDHCI_CLOCK_CARD_EN; 386 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 387 388 host->clock = clock; 389 return 0; 390 } 391 392 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 393 { 394 u8 pwr = 0; 395 396 if (power != (unsigned short)-1) { 397 switch (1 << power) { 398 case MMC_VDD_165_195: 399 pwr = SDHCI_POWER_180; 400 break; 401 case MMC_VDD_29_30: 402 case MMC_VDD_30_31: 403 pwr = SDHCI_POWER_300; 404 break; 405 case MMC_VDD_32_33: 406 case MMC_VDD_33_34: 407 pwr = SDHCI_POWER_330; 408 break; 409 } 410 } 411 412 if (pwr == 0) { 413 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 414 return; 415 } 416 417 pwr |= SDHCI_POWER_ON; 418 419 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 420 } 421 422 static void sdhci_set_uhs_signaling(struct sdhci_host *host) 423 { 424 u16 ctrl_2; 425 u32 timing = host->mmc->timing; 426 427 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 428 /* Select Bus Speed Mode for host */ 429 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 430 431 if ((timing != MMC_TIMING_LEGACY) && 432 (timing != MMC_TIMING_MMC_HS) && 433 (timing != MMC_TIMING_SD_HS)) 434 ctrl_2 |= SDHCI_CTRL_VDD_180; 435 436 if ((timing == MMC_TIMING_MMC_HS200) || 437 (timing == MMC_TIMING_UHS_SDR104)) 438 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A; 439 else if (timing == MMC_TIMING_UHS_SDR12) 440 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 441 else if (timing == MMC_TIMING_UHS_SDR25) 442 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 443 else if (timing == MMC_TIMING_UHS_SDR50) 444 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 445 else if ((timing == MMC_TIMING_UHS_DDR50) || 446 (timing == MMC_TIMING_MMC_DDR52)) 447 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 448 else if (timing == MMC_TIMING_MMC_HS400 || 449 timing == MMC_TIMING_MMC_HS400ES) 450 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A; 451 452 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 453 } 454 455 #ifdef CONFIG_DM_MMC 456 static bool sdhci_card_busy(struct udevice *dev) 457 { 458 struct mmc *mmc = mmc_get_mmc_dev(dev); 459 #else 460 static bool sdhci_card_busy(struct mmc *mmc) 461 { 462 #endif 463 struct sdhci_host *host = mmc->priv; 464 u32 present_state; 465 466 /* Check whether DAT[0] is 0 */ 467 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 468 469 return !(present_state & SDHCI_DATA_0_LVL); 470 } 471 472 #ifdef CONFIG_DM_MMC 473 static int sdhci_set_ios(struct udevice *dev) 474 { 475 struct mmc *mmc = mmc_get_mmc_dev(dev); 476 #else 477 static int sdhci_set_ios(struct mmc *mmc) 478 { 479 #endif 480 u32 ctrl; 481 struct sdhci_host *host = mmc->priv; 482 483 if (host->ops && host->ops->set_control_reg) 484 host->ops->set_control_reg(host); 485 486 if (mmc->clock != host->clock) { 487 if (host->ops && host->ops->set_clock) 488 host->ops->set_clock(host, mmc->clock); 489 else 490 sdhci_set_clock(host, mmc->clock); 491 } 492 493 /* Set bus width */ 494 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 495 if (mmc->bus_width == 8) { 496 ctrl &= ~SDHCI_CTRL_4BITBUS; 497 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 498 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 499 ctrl |= SDHCI_CTRL_8BITBUS; 500 } else { 501 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 502 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 503 ctrl &= ~SDHCI_CTRL_8BITBUS; 504 if (mmc->bus_width == 4) 505 ctrl |= SDHCI_CTRL_4BITBUS; 506 else 507 ctrl &= ~SDHCI_CTRL_4BITBUS; 508 } 509 510 if (!(mmc->timing == MMC_TIMING_LEGACY) && 511 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 512 ctrl |= SDHCI_CTRL_HISPD; 513 else 514 ctrl &= ~SDHCI_CTRL_HISPD; 515 516 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 517 518 if ((mmc->timing != MMC_TIMING_LEGACY) && 519 (mmc->timing != MMC_TIMING_MMC_HS) && 520 (mmc->timing != MMC_TIMING_SD_HS)) 521 sdhci_set_power(host, MMC_VDD_165_195_SHIFT); 522 523 sdhci_set_uhs_signaling(host); 524 525 /* If available, call the driver specific "post" set_ios() function */ 526 if (host->ops && host->ops->set_ios_post) 527 host->ops->set_ios_post(host); 528 529 return 0; 530 } 531 532 static int sdhci_init(struct mmc *mmc) 533 { 534 struct sdhci_host *host = mmc->priv; 535 536 sdhci_reset(host, SDHCI_RESET_ALL); 537 538 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 539 aligned_buffer = memalign(8, 512*1024); 540 if (!aligned_buffer) { 541 printf("%s: Aligned buffer alloc failed!!!\n", 542 __func__); 543 return -ENOMEM; 544 } 545 } 546 547 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 548 549 if (host->ops && host->ops->get_cd) 550 host->ops->get_cd(host); 551 552 /* Enable only interrupts served by the SD controller */ 553 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 554 SDHCI_INT_ENABLE); 555 /* Mask all sdhci interrupt sources */ 556 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 557 558 return 0; 559 } 560 561 #ifdef CONFIG_DM_MMC 562 int sdhci_probe(struct udevice *dev) 563 { 564 struct mmc *mmc = mmc_get_mmc_dev(dev); 565 566 return sdhci_init(mmc); 567 } 568 569 const struct dm_mmc_ops sdhci_ops = { 570 .card_busy = sdhci_card_busy, 571 .send_cmd = sdhci_send_command, 572 .set_ios = sdhci_set_ios, 573 }; 574 #else 575 static const struct mmc_ops sdhci_ops = { 576 .card_busy = sdhci_card_busy, 577 .send_cmd = sdhci_send_command, 578 .set_ios = sdhci_set_ios, 579 .init = sdhci_init, 580 }; 581 #endif 582 583 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 584 u32 f_max, u32 f_min) 585 { 586 u32 caps, caps_1; 587 588 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 589 590 #ifdef CONFIG_MMC_SDHCI_SDMA 591 if (!(caps & SDHCI_CAN_DO_SDMA)) { 592 printf("%s: Your controller doesn't support SDMA!!\n", 593 __func__); 594 return -EINVAL; 595 } 596 #endif 597 if (host->quirks & SDHCI_QUIRK_REG32_RW) 598 host->version = 599 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 600 else 601 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 602 603 cfg->name = host->name; 604 #ifndef CONFIG_DM_MMC 605 cfg->ops = &sdhci_ops; 606 #endif 607 608 /* Check whether the clock multiplier is supported or not */ 609 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 610 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 611 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 612 SDHCI_CLOCK_MUL_SHIFT; 613 } 614 615 if (host->max_clk == 0) { 616 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 617 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 618 SDHCI_CLOCK_BASE_SHIFT; 619 else 620 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 621 SDHCI_CLOCK_BASE_SHIFT; 622 host->max_clk *= 1000000; 623 if (host->clk_mul) 624 host->max_clk *= host->clk_mul; 625 } 626 if (host->max_clk == 0) { 627 printf("%s: Hardware doesn't specify base clock frequency\n", 628 __func__); 629 return -EINVAL; 630 } 631 if (f_max && (f_max < host->max_clk)) 632 cfg->f_max = f_max; 633 else 634 cfg->f_max = host->max_clk; 635 if (f_min) 636 cfg->f_min = f_min; 637 else { 638 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 639 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 640 else 641 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 642 } 643 cfg->voltages = 0; 644 if (caps & SDHCI_CAN_VDD_330) 645 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 646 if (caps & SDHCI_CAN_VDD_300) 647 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 648 if (caps & SDHCI_CAN_VDD_180) 649 cfg->voltages |= MMC_VDD_165_195; 650 651 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 652 cfg->voltages |= host->voltages; 653 654 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 655 656 /* Since Host Controller Version3.0 */ 657 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 658 if (!(caps & SDHCI_CAN_DO_8BIT)) 659 cfg->host_caps &= ~MMC_MODE_8BIT; 660 } 661 662 if (host->host_caps) 663 cfg->host_caps |= host->host_caps; 664 665 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 666 667 return 0; 668 } 669 670 #ifdef CONFIG_BLK 671 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 672 { 673 return mmc_bind(dev, mmc, cfg); 674 } 675 #else 676 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 677 { 678 int ret; 679 680 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 681 if (ret) 682 return ret; 683 684 host->mmc = mmc_create(&host->cfg, host); 685 if (host->mmc == NULL) { 686 printf("%s: mmc create fail!\n", __func__); 687 return -ENOMEM; 688 } 689 690 return 0; 691 } 692 #endif 693