1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <div64.h> 15 16 static struct rockchip_pll_rate_table rockchip_auto_table; 17 18 #define PLL_MODE_MASK 0x3 19 #define PLL_RK3328_MODE_MASK 0x1 20 21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 22 #define RK3036_PLLCON0_FBDIV_SHIFT 0 23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12 24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 26 #define RK3036_PLLCON1_REFDIV_SHIFT 0 27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6 28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12 30 #define RK3036_PLLCON1_DSMPD_SHIFT 12 31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 32 #define RK3036_PLLCON2_FRAC_SHIFT 0 33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13 34 35 #define MHZ 1000000 36 #define KHZ 1000 37 enum { 38 OSC_HZ = 24 * 1000000, 39 VCO_MAX_HZ = 3200U * 1000000, 40 VCO_MIN_HZ = 800 * 1000000, 41 OUTPUT_MAX_HZ = 3200U * 1000000, 42 OUTPUT_MIN_HZ = 24 * 1000000, 43 RK3588_VCO_MIN_HZ = 2250U * 1000000, 44 RK3588_VCO_MAX_HZ = 4500U * 1000000, 45 RK3588_FOUT_MIN_HZ = 37U * 1000000, 46 RK3588_FOUT_MAX_HZ = 4500U * 1000000, 47 }; 48 49 #define MIN_FOUTVCO_FREQ (800 * MHZ) 50 #define MAX_FOUTVCO_FREQ (2000 * MHZ) 51 52 int gcd(int m, int n) 53 { 54 int t; 55 56 while (m > 0) { 57 if (n > m) { 58 t = m; 59 m = n; 60 n = t; 61 } /* swap */ 62 m -= n; 63 } 64 return n; 65 } 66 67 /* 68 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 69 * Formulas also embedded within the Fractional PLL Verilog model: 70 * If DSMPD = 1 (DSM is disabled, "integer mode") 71 * FOUTVCO = FREF / REFDIV * FBDIV 72 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 73 * Where: 74 * FOUTVCO = Fractional PLL non-divided output frequency 75 * FOUTPOSTDIV = Fractional PLL divided output frequency 76 * (output of second post divider) 77 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 78 * REFDIV = Fractional PLL input reference clock divider 79 * FBDIV = Integer value programmed into feedback divide 80 * 81 */ 82 83 static int rockchip_pll_clk_set_postdiv(ulong fout_hz, 84 u32 *postdiv1, 85 u32 *postdiv2, 86 u32 *foutvco) 87 { 88 ulong freq; 89 90 if (fout_hz < MIN_FOUTVCO_FREQ) { 91 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { 92 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 93 freq = fout_hz * (*postdiv1) * (*postdiv2); 94 if (freq >= MIN_FOUTVCO_FREQ && 95 freq <= MAX_FOUTVCO_FREQ) { 96 *foutvco = freq; 97 return 0; 98 } 99 } 100 } 101 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n", 102 fout_hz); 103 } else { 104 *postdiv1 = 1; 105 *postdiv2 = 1; 106 } 107 return 0; 108 } 109 110 static struct rockchip_pll_rate_table * 111 rockchip_pll_clk_set_by_auto(ulong fin_hz, 112 ulong fout_hz) 113 { 114 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 115 /* FIXME set postdiv1/2 always 1*/ 116 u32 foutvco = fout_hz; 117 ulong fin_64, frac_64; 118 u32 f_frac, postdiv1, postdiv2; 119 ulong clk_gcd = 0; 120 121 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 122 return NULL; 123 124 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 125 rate_table->postdiv1 = postdiv1; 126 rate_table->postdiv2 = postdiv2; 127 rate_table->dsmpd = 1; 128 129 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 130 fin_hz /= MHZ; 131 foutvco /= MHZ; 132 clk_gcd = gcd(fin_hz, foutvco); 133 rate_table->refdiv = fin_hz / clk_gcd; 134 rate_table->fbdiv = foutvco / clk_gcd; 135 136 rate_table->frac = 0; 137 138 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n", 139 fin_hz, fout_hz, clk_gcd); 140 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n", 141 rate_table->refdiv, 142 rate_table->fbdiv, rate_table->postdiv1, 143 rate_table->postdiv2); 144 } else { 145 debug("frac div,fin_hz = %ld,fout_hz = %ld\n", 146 fin_hz, fout_hz); 147 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n", 148 rate_table->postdiv1, rate_table->postdiv2, foutvco); 149 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ); 150 rate_table->refdiv = fin_hz / MHZ / clk_gcd; 151 rate_table->fbdiv = foutvco / MHZ / clk_gcd; 152 debug("frac get refdiv = %d, fbdiv = %d\n", 153 rate_table->refdiv, rate_table->fbdiv); 154 155 rate_table->frac = 0; 156 157 f_frac = (foutvco % MHZ); 158 fin_64 = fin_hz; 159 fin_64 = fin_64 / rate_table->refdiv; 160 frac_64 = f_frac << 24; 161 frac_64 = frac_64 / fin_64; 162 rate_table->frac = frac_64; 163 if (rate_table->frac > 0) 164 rate_table->dsmpd = 0; 165 debug("frac = %x\n", rate_table->frac); 166 } 167 return rate_table; 168 } 169 170 static struct rockchip_pll_rate_table * 171 rk3588_pll_clk_set_by_auto(unsigned long fin_hz, 172 unsigned long fout_hz) 173 { 174 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; 175 u32 p, m, s; 176 ulong fvco, fref, fout, ffrac; 177 178 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) 179 return NULL; 180 181 if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) 182 return NULL; 183 184 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { 185 for (s = 0; s <= 6; s++) { 186 fvco = fout_hz << s; 187 if (fvco < RK3588_VCO_MIN_HZ || 188 fvco > RK3588_VCO_MAX_HZ) 189 continue; 190 for (p = 2; p <= 4; p++) { 191 for (m = 64; m <= 1023; m++) { 192 if (fvco == m * fin_hz / p) { 193 rate_table->p = p; 194 rate_table->m = m; 195 rate_table->s = s; 196 rate_table->k = 0; 197 return rate_table; 198 } 199 } 200 } 201 } 202 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 203 } else { 204 fout = (fout_hz / MHZ) * MHZ; 205 ffrac = (fout_hz % MHZ); 206 for (s = 0; s <= 6; s++) { 207 fvco = fout << s; 208 if (fvco < RK3588_VCO_MIN_HZ || 209 fvco > RK3588_VCO_MAX_HZ) 210 continue; 211 for (p = 1; p <= 4; p++) { 212 for (m = 64; m <= 1023; m++) { 213 if (fvco == m * fin_hz / p) { 214 rate_table->p = p; 215 rate_table->m = m; 216 rate_table->s = s; 217 fref = fin_hz / p; 218 fout = (ffrac << s) * 65535; 219 rate_table->k = fout / fref; 220 return rate_table; 221 } 222 } 223 } 224 } 225 pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); 226 } 227 return NULL; 228 } 229 230 static const struct rockchip_pll_rate_table * 231 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) 232 { 233 struct rockchip_pll_rate_table *rate_table = pll->rate_table; 234 235 while (rate_table->rate) { 236 if (rate_table->rate == rate) 237 break; 238 rate_table++; 239 } 240 if (rate_table->rate != rate) { 241 if (pll->type == pll_rk3588) 242 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 243 else 244 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 245 } else { 246 return rate_table; 247 } 248 } 249 250 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, 251 void __iomem *base, ulong pll_id, 252 ulong drate) 253 { 254 const struct rockchip_pll_rate_table *rate; 255 256 rate = rockchip_get_pll_settings(pll, drate); 257 if (!rate) { 258 printf("%s unsupport rate\n", __func__); 259 return -EINVAL; 260 } 261 262 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n", 263 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); 264 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n", 265 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); 266 267 /* 268 * When power on or changing PLL setting, 269 * we must force PLL into slow mode to ensure output stable clock. 270 */ 271 rk_clrsetreg(base + pll->mode_offset, 272 pll->mode_mask << pll->mode_shift, 273 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 274 275 /* Power down */ 276 rk_setreg(base + pll->con_offset + 0x4, 277 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 278 279 rk_clrsetreg(base + pll->con_offset, 280 (RK3036_PLLCON0_POSTDIV1_MASK | 281 RK3036_PLLCON0_FBDIV_MASK), 282 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | 283 rate->fbdiv); 284 rk_clrsetreg(base + pll->con_offset + 0x4, 285 (RK3036_PLLCON1_POSTDIV2_MASK | 286 RK3036_PLLCON1_REFDIV_MASK), 287 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | 288 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); 289 if (!rate->dsmpd) { 290 rk_clrsetreg(base + pll->con_offset + 0x4, 291 RK3036_PLLCON1_DSMPD_MASK, 292 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); 293 writel((readl(base + pll->con_offset + 0x8) & 294 (~RK3036_PLLCON2_FRAC_MASK)) | 295 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), 296 base + pll->con_offset + 0x8); 297 } 298 299 /* Power Up */ 300 rk_clrreg(base + pll->con_offset + 0x4, 301 1 << RK3036_PLLCON1_PWRDOWN_SHIT); 302 303 /* waiting for pll lock */ 304 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { 305 udelay(1); 306 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 307 } 308 309 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 310 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 311 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 312 pll, readl(base + pll->con_offset), 313 readl(base + pll->con_offset + 0x4), 314 readl(base + pll->con_offset + 0x8), 315 readl(base + pll->mode_offset)); 316 317 return 0; 318 } 319 320 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, 321 void __iomem *base, ulong pll_id) 322 { 323 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; 324 u32 con = 0, shift, mask; 325 ulong rate; 326 327 con = readl(base + pll->mode_offset); 328 shift = pll->mode_shift; 329 mask = pll->mode_mask << shift; 330 331 switch ((con & mask) >> shift) { 332 case RKCLK_PLL_MODE_SLOW: 333 return OSC_HZ; 334 case RKCLK_PLL_MODE_NORMAL: 335 /* normal mode */ 336 con = readl(base + pll->con_offset); 337 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 338 RK3036_PLLCON0_POSTDIV1_SHIFT; 339 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 340 RK3036_PLLCON0_FBDIV_SHIFT; 341 con = readl(base + pll->con_offset + 0x4); 342 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 343 RK3036_PLLCON1_POSTDIV2_SHIFT; 344 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 345 RK3036_PLLCON1_REFDIV_SHIFT; 346 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> 347 RK3036_PLLCON1_DSMPD_SHIFT; 348 con = readl(base + pll->con_offset + 0x8); 349 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> 350 RK3036_PLLCON2_FRAC_SHIFT; 351 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 352 if (dsmpd == 0) { 353 u64 frac_rate = OSC_HZ * (u64)frac; 354 355 do_div(frac_rate, refdiv); 356 frac_rate >>= 24; 357 do_div(frac_rate, postdiv1); 358 do_div(frac_rate, postdiv1); 359 rate += frac_rate; 360 } 361 return rate; 362 case RKCLK_PLL_MODE_DEEP: 363 default: 364 return 32768; 365 } 366 } 367 368 #define RK3588_PLLCON(i) ((i) * 0x4) 369 #define RK3588_PLLCON0_M_MASK 0x3ff << 0 370 #define RK3588_PLLCON0_M_SHIFT 0 371 #define RK3588_PLLCON1_P_MASK 0x3f << 0 372 #define RK3588_PLLCON1_P_SHIFT 0 373 #define RK3588_PLLCON1_S_MASK 0x7 << 6 374 #define RK3588_PLLCON1_S_SHIFT 6 375 #define RK3588_PLLCON2_K_MASK 0xffff 376 #define RK3588_PLLCON2_K_SHIFT 0 377 #define RK3588_PLLCON1_PWRDOWN BIT(13) 378 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 379 #define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) 380 #define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) 381 #define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) 382 383 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, 384 void __iomem *base, ulong pll_id, 385 ulong drate) 386 { 387 const struct rockchip_pll_rate_table *rate; 388 389 rate = rockchip_get_pll_settings(pll, drate); 390 if (!rate) { 391 printf("%s unsupported rate\n", __func__); 392 return -EINVAL; 393 } 394 395 debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 396 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 397 398 /* 399 * When power on or changing PLL setting, 400 * we must force PLL into slow mode to ensure output stable clock. 401 */ 402 rk_clrsetreg(base + pll->mode_offset, 403 pll->mode_mask << pll->mode_shift, 404 RKCLK_PLL_MODE_SLOW << pll->mode_shift); 405 if (pll_id == 0) 406 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 407 pll->mode_mask << 6, 408 RKCLK_PLL_MODE_SLOW << 6); 409 else if (pll_id == 1) 410 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), 411 pll->mode_mask << 6, 412 RKCLK_PLL_MODE_SLOW << 6); 413 else if (pll_id == 2) 414 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 415 pll->mode_mask << 14, 416 RKCLK_PLL_MODE_SLOW << 14); 417 418 /* Power down */ 419 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), 420 RK3588_PLLCON1_PWRDOWN); 421 422 rk_clrsetreg(base + pll->con_offset, 423 RK3588_PLLCON0_M_MASK, 424 (rate->m << RK3588_PLLCON0_M_SHIFT)); 425 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), 426 (RK3588_PLLCON1_P_MASK | 427 RK3588_PLLCON1_S_MASK), 428 (rate->p << RK3588_PLLCON1_P_SHIFT | 429 rate->s << RK3588_PLLCON1_S_SHIFT)); 430 if (!rate->k) { 431 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), 432 RK3588_PLLCON2_K_MASK, 433 rate->k << RK3588_PLLCON2_K_SHIFT); 434 } 435 /* Power up */ 436 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), 437 RK3588_PLLCON1_PWRDOWN); 438 439 /* waiting for pll lock */ 440 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & 441 RK3588_PLLCON6_LOCK_STATUS)) { 442 udelay(1); 443 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); 444 } 445 446 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, 447 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); 448 if (pll_id == 0) 449 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 450 pll->mode_mask << 6, 451 2 << 6); 452 else if (pll_id == 1) 453 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), 454 pll->mode_mask << 6, 455 2 << 6); 456 else if (pll_id == 2) 457 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), 458 pll->mode_mask << 14, 459 2 << 14); 460 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", 461 pll, readl(base + pll->con_offset), 462 readl(base + pll->con_offset + 0x4), 463 readl(base + pll->con_offset + 0x8), 464 readl(base + pll->mode_offset)); 465 466 return 0; 467 } 468 469 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, 470 void __iomem *base, ulong pll_id) 471 { 472 u32 m, p, s, k; 473 u32 con = 0, shift, mode; 474 u64 rate, postdiv; 475 476 con = readl(base + pll->mode_offset); 477 shift = pll->mode_shift; 478 if (pll_id == 8) 479 mode = RKCLK_PLL_MODE_NORMAL; 480 else 481 mode = (con & (pll->mode_mask << shift)) >> shift; 482 switch (mode) { 483 case RKCLK_PLL_MODE_SLOW: 484 return OSC_HZ; 485 case RKCLK_PLL_MODE_NORMAL: 486 /* normal mode */ 487 con = readl(base + pll->con_offset); 488 m = (con & RK3588_PLLCON0_M_MASK) >> 489 RK3588_PLLCON0_M_SHIFT; 490 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); 491 p = (con & RK3588_PLLCON1_P_MASK) >> 492 RK3036_PLLCON0_FBDIV_SHIFT; 493 s = (con & RK3588_PLLCON1_S_MASK) >> 494 RK3588_PLLCON1_S_SHIFT; 495 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); 496 k = (con & RK3588_PLLCON2_K_MASK) >> 497 RK3588_PLLCON2_K_SHIFT; 498 499 rate = OSC_HZ / p; 500 rate *= m; 501 if (k) { 502 /* fractional mode */ 503 u64 frac_rate64 = OSC_HZ * k; 504 505 postdiv = p * 65535; 506 do_div(frac_rate64, postdiv); 507 rate += frac_rate64; 508 } 509 rate = rate >> s; 510 return rate; 511 case RKCLK_PLL_MODE_DEEP: 512 default: 513 return 32768; 514 } 515 } 516 517 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 518 void __iomem *base, 519 ulong pll_id) 520 { 521 ulong rate = 0; 522 523 switch (pll->type) { 524 case pll_rk3036: 525 pll->mode_mask = PLL_MODE_MASK; 526 rate = rk3036_pll_get_rate(pll, base, pll_id); 527 break; 528 case pll_rk3328: 529 pll->mode_mask = PLL_RK3328_MODE_MASK; 530 rate = rk3036_pll_get_rate(pll, base, pll_id); 531 break; 532 case pll_rk3588: 533 pll->mode_mask = PLL_MODE_MASK; 534 rate = rk3588_pll_get_rate(pll, base, pll_id); 535 break; 536 default: 537 printf("%s: Unknown pll type for pll clk %ld\n", 538 __func__, pll_id); 539 } 540 return rate; 541 } 542 543 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 544 void __iomem *base, ulong pll_id, 545 ulong drate) 546 { 547 int ret = 0; 548 549 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) 550 return 0; 551 552 switch (pll->type) { 553 case pll_rk3036: 554 pll->mode_mask = PLL_MODE_MASK; 555 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 556 break; 557 case pll_rk3328: 558 pll->mode_mask = PLL_RK3328_MODE_MASK; 559 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); 560 break; 561 case pll_rk3588: 562 pll->mode_mask = PLL_MODE_MASK; 563 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); 564 break; 565 default: 566 printf("%s: Unknown pll type for pll clk %ld\n", 567 __func__, pll_id); 568 } 569 return ret; 570 } 571 572 const struct rockchip_cpu_rate_table * 573 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 574 ulong rate) 575 { 576 struct rockchip_cpu_rate_table *ps = cpu_table; 577 578 while (ps->rate) { 579 if (ps->rate == rate) 580 break; 581 ps++; 582 } 583 if (ps->rate != rate) 584 return NULL; 585 else 586 return ps; 587 } 588 589