rockchip: Add arch timer 1Ghz support

Change-Id: I8e58b15be1823e732852a2aa76cc98813e6b4fe9
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

spl/uboot: Add build tag verbose

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I2f6c1b82545efd815bfa161c962743cf35d48b54

common: Add MP boot support

mp_boot build from: a5185c920.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8f8b2fe45ee87ad0a60e1dfd6f0950f052d4f1e7

spl: print generic timer ticks

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib7a24b4ef8fb4d187faa6a028d133c291296e092

spl: support bring up kernel with macro CONFIG_SPL_KERNEL_BOOT

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Icdf16172a197d04627c1cb396cc5feb3723e0dbf

spl: cleanup before jump to U-Boot

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I32cc543bc65a3d1a5e889b9baf75b1ea6bbb0149

spl: enable U-Boot jump message

This is friendly for us to know what SPL does.

RV1126 boot message:

U-Boot SPL 2017.09-g4f0c5b5663-220210-dirty #cjh (Feb 15 2022 - 02:10:33)
......
## Verifi

spl: enable U-Boot jump message

This is friendly for us to know what SPL does.

RV1126 boot message:

U-Boot SPL 2017.09-g4f0c5b5663-220210-dirty #cjh (Feb 15 2022 - 02:10:33)
......
## Verified-boot: 0
## Checking uboot 0x00600000 ... sha256(3d716084f7...) + OK
## Checking fdt 0x006ba8e0 ... sha256(80f00e7967...) + OK
Jumping to U-Boot(0x00600000)

U-Boot 2017.09-g4f0c5b5663-220210-dirty #cjh (Feb 15 2022 - 02:11:31 +0000)

Model: Rockchip RV1126 Evaluation Board
PreSerial: 2, raw, 0xff570000
......

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I27f97924a22563b872a47bafffbf2fc9c749c9db

show more ...

spl: add spl_board_storages_fixup()

This function may be used to fix storages problem, like iomux.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ia4d7cd3374ec1f97f052b7359c7e6f616e

spl: add spl_board_storages_fixup()

This function may be used to fix storages problem, like iomux.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ia4d7cd3374ec1f97f052b7359c7e6f616e986c99

show more ...

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene ===
When access a illegal address, It results in:
- read: Synchronous data-abort
- write: SError(64-bit)/Asynchronous external abort(32-bit)

=== 64-bit ===
EL3 SError ASynchronous exception in TPL/SPL was already
enabled in start.S and crt0_64.S which sets SCR_EL3.EA=1
and DAIF.A=0. We can test result of TPL/SPL by access address
0xfe108000 in rk3568.
Let's enable SError in U-Boot proper.

=== 32-bit ===
Let's set CPSR.A=0 to enable Asynchronous external abort, we can
test result by access address 0xfe808000 in rv1126.
Note: TPL/SPL vectors only provides "b ." for all exception entry.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id9f660a9275f69fdc8443ad239aabf79682d95d0

show more ...

spl: modify the spl log

Correct the log when bring up kernel with spl directly.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic3204d8ddab37c3a5aac3488e209b3764e96a977

spl: fit: print ATF and U-Boot load address

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I0b732934c1aa63ed6e849d85bd77fa8ec1f622b3

common: spl: show total time of SPL

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I93de59f4064a2579f8010da2655607f45840f8ed

common: spl: initial spl->next_stage

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5066612be4c90ff674b61034768eeaba9b9c9b85

Merge branch 'next-dev' into thunder-boot

common: spl: change TLB memory base align to SZ_16K

According to armv7 spec, translation table base 0 address is align to
2^(14-n). The n is set by TTBCR and is set to zero in uboot.

Signed-off-by:

common: spl: change TLB memory base align to SZ_16K

According to armv7 spec, translation table base 0 address is align to
2^(14-n). The n is set by TTBCR and is set to zero in uboot.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3d4c3f7165d3ef27bcc51d90471830f5e6dccae5

show more ...

Merge branch 'next-dev' into thunder-boot

spl: print entry point for U-Boot and OP-TEE

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ifeb52986851b93cb634f177e3834cbf681f3dfb0

Merge branch 'next-dev' into thunder-boot

spl: do cleanup before jumping to next stage

Cache/mmu/interrupt cleanup is recommand before jumping to
next stage to avoid some uncertain things.

Provide a arch/board-specific callback to do clean

spl: do cleanup before jumping to next stage

Cache/mmu/interrupt cleanup is recommand before jumping to
next stage to avoid some uncertain things.

Provide a arch/board-specific callback to do cleanup things.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5e4e378ec9080e7af283741370bcd9c2dc897dc

show more ...

Merge branch 'next-dev' into thunder-boot

Conflicts:
common/spl/spl_rkfw.c
drivers/pinctrl/pinctrl-rockchip.c
make.sh

Change-Id: I93f4dbe1e067c3b938bf64c4964bd5e7023b1daf
Signed-off-by: Joseph C

Merge branch 'next-dev' into thunder-boot

Conflicts:
common/spl/spl_rkfw.c
drivers/pinctrl/pinctrl-rockchip.c
make.sh

Change-Id: I93f4dbe1e067c3b938bf64c4964bd5e7023b1daf
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...

common: spl: set default address for entry_point_os

Could be override in boot_from_devices().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ifbfac5903ec61e65739732949f9e6b8a2704155d

common: spl: set default address for entry_point_os

Could be override in boot_from_devices().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ifbfac5903ec61e65739732949f9e6b8a2704155d
(cherry picked from commit f8ca32e1ca9a3df6a1e6fb6997721307c33f354e)

show more ...

common: spl: jump next process depend on entry_point_os

The spl can bring up uboot & kernel, and their entry points are diffirent,
so pass their entry points by entry_point_os.

Signed-off-by: Jason

common: spl: jump next process depend on entry_point_os

The spl can bring up uboot & kernel, and their entry points are diffirent,
so pass their entry points by entry_point_os.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I625d135d219cfbfb620ff1e3d0de5278143f4079
(cherry picked from commit 78628ac9a95ec2bb6bffa049323beb6af3eb3f37)

show more ...

common: spl: call the spl_next_stage() to get next stage process

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ibfe81766fcbfe002978b7d225a5602a8eeb89c12

Merge branch 'next-dev' into thunder-boot

common: spl: set default address for entry_point_os

Could be override in boot_from_devices().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ifbfac5903ec61e65739732949f9e6b8a2704155d