| e3f40720 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Support both SF and eMMC SoMs
Discern the SoMs based on the presence of SPI flash to support both
variants of the SoM, one booting from SPI NOR and one booting from
eMMC.
Signed-o
ARM: at91: ma5d4: Support both SF and eMMC SoMs
Discern the SoMs based on the presence of SPI flash to support both
variants of the SoM, one booting from SPI NOR and one booting from
eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
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| 8997de29 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Boot from MMC2 when using SAM-BA
Continue loading U-Boot from MMC2 when the SPL was loaded using SAM-BA
loader. This allows the board to boot system from the removable media
instea
ARM: at91: ma5d4: Boot from MMC2 when using SAM-BA
Continue loading U-Boot from MMC2 when the SPL was loaded using SAM-BA
loader. This allows the board to boot system from the removable media
instead of the eMMC, which is useful for commissioning purposes. When
booting from the eMMC, always boot from it as it is not possible to
boot from the SD interface directly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
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| 4425be39 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Swap SD/MMC controller order
The SDHCI1 is the primary boot controller on rev. 2.1 SoM, which
is the version available on the market. Swap the controller order
to match this and fu
ARM: at91: ma5d4: Swap SD/MMC controller order
The SDHCI1 is the primary boot controller on rev. 2.1 SoM, which
is the version available on the market. Swap the controller order
to match this and future versions of the SoM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
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| 24257db0 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Init SD/MMC controller in SPL
Init the controllers, otherwise the board cannot boot from SD/MMC.
This boot option is new on rev. 2.1 SoM .
Signed-off-by: Marek Vasut <marex@denx.d
ARM: at91: ma5d4: Init SD/MMC controller in SPL
Init the controllers, otherwise the board cannot boot from SD/MMC.
This boot option is new on rev. 2.1 SoM .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
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| 52a557d6 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Reset CAN controllers late
The CAN controllers need slight delay between toggling of their reset
line. Move this action into board_init(), otherwise timer will not be
initialized a
ARM: at91: ma5d4: Reset CAN controllers late
The CAN controllers need slight delay between toggling of their reset
line. Move this action into board_init(), otherwise timer will not be
initialized and the board might hang.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
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| ae625ae5 | 02-May-2017 |
Marek Vasut <marex@denx.de> |
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Inc
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
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