| d3b884b2 | 20-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and table setup. Put this code in a common function so it can be used by those drivers
dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and table setup. Put this code in a common function so it can be used by those drivers that want it.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| f60df20a | 07-Jan-2016 |
Miao Yan <yanmiaobest@gmail.com> |
x86: qemu: add fw_cfg support
The QEMU fw_cfg interface allows the guest to retrieve various data information from QEMU. For example, APCI/SMBios tables, number of online cpus, kernel data and comma
x86: qemu: add fw_cfg support
The QEMU fw_cfg interface allows the guest to retrieve various data information from QEMU. For example, APCI/SMBios tables, number of online cpus, kernel data and command line, etc.
This patch adds support for QEMU fw_cfg interface.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| 4ce022d3 | 11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that does not fol
x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that does not follow 1.0 spec (possible due to that FSP predates the 1.0 spec), and future FSP binary that is complaint to v1.1 spec defines an optional paltform-specific runtime data in the struct fspinit_rtbuf. Hence move the definition to chipset header.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 81f84aa6 | 11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: fsp: Rename update_fsp_upd() and change its signature
To support platform-specific configurations (might not always be UPD on some platform), use a better name update_fsp_configs() and accepct
x86: fsp: Rename update_fsp_upd() and change its signature
To support platform-specific configurations (might not always be UPD on some platform), use a better name update_fsp_configs() and accepct struct fsp_config_data as its parameter so that platform codes can handle whatever configuration data for that FSP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
| cb379a34 | 11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: fsp: Rename shared_data to fsp_config_data
FSP has several config data like UPD, HDA verb table which can be overridden or provided by bootloader. Currently in U-Boot only UPD is handled via st
x86: fsp: Rename shared_data to fsp_config_data
FSP has several config data like UPD, HDA verb table which can be overridden or provided by bootloader. Currently in U-Boot only UPD is handled via struct shared_data. To accommodate any platform, we rename shared_data to fsp_config_data and move the definition from common place fsp_support.h to platform-specific place fsp_configs.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
| e5ffa4bb | 23-Oct-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA dis
x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses.
However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work.
To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|