1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <fdtdec.h> 18 #include <asm/cpu.h> 19 #include <asm/io.h> 20 #include <asm/lapic.h> 21 #include <asm/msr.h> 22 #include <asm/mtrr.h> 23 #include <asm/pci.h> 24 #include <asm/post.h> 25 #include <asm/processor.h> 26 #include <asm/arch/model_206ax.h> 27 #include <asm/arch/microcode.h> 28 #include <asm/arch/pch.h> 29 #include <asm/arch/sandybridge.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) 34 { 35 /* Enable port 80 POST on LPC */ 36 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 37 clrbits_le32(RCB_REG(GCS), 4); 38 } 39 40 /* 41 * Enable Prefetching and Caching. 42 */ 43 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) 44 { 45 u8 reg8; 46 47 pci_hose_read_config_byte(hose, dev, 0xdc, ®8); 48 reg8 &= ~(3 << 2); 49 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 50 pci_hose_write_config_byte(hose, dev, 0xdc, reg8); 51 } 52 53 static int set_flex_ratio_to_tdp_nominal(void) 54 { 55 msr_t flex_ratio, msr; 56 u8 nominal_ratio; 57 58 /* Minimum CPU revision for configurable TDP support */ 59 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 60 return -EINVAL; 61 62 /* Check for Flex Ratio support */ 63 flex_ratio = msr_read(MSR_FLEX_RATIO); 64 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 65 return -EINVAL; 66 67 /* Check for >0 configurable TDPs */ 68 msr = msr_read(MSR_PLATFORM_INFO); 69 if (((msr.hi >> 1) & 3) == 0) 70 return -EINVAL; 71 72 /* Use nominal TDP ratio for flex ratio */ 73 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 74 nominal_ratio = msr.lo & 0xff; 75 76 /* See if flex ratio is already set to nominal TDP ratio */ 77 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 78 return 0; 79 80 /* Set flex ratio to nominal TDP ratio */ 81 flex_ratio.lo &= ~0xff00; 82 flex_ratio.lo |= nominal_ratio << 8; 83 flex_ratio.lo |= FLEX_RATIO_LOCK; 84 msr_write(MSR_FLEX_RATIO, flex_ratio); 85 86 /* Set flex ratio in soft reset data register bits 11:6 */ 87 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 88 (nominal_ratio & 0x3f) << 6); 89 90 /* Set soft reset control to use register value */ 91 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 92 93 /* Issue warm reset, will be "CPU only" due to soft reset data */ 94 outb(0x0, PORT_RESET); 95 outb(SYS_RST | RST_CPU, PORT_RESET); 96 cpu_hlt(); 97 98 /* Not reached */ 99 return -EINVAL; 100 } 101 102 static void set_spi_speed(void) 103 { 104 u32 fdod; 105 106 /* Observe SPI Descriptor Component Section 0 */ 107 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 108 109 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 110 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 111 fdod >>= 24; 112 fdod &= 7; 113 114 /* Set Software Sequence frequency to match */ 115 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 116 } 117 118 int arch_cpu_init(void) 119 { 120 post_code(POST_CPU_INIT); 121 122 return x86_cpu_init_f(); 123 } 124 125 int arch_cpu_init_dm(void) 126 { 127 struct pci_controller *hose; 128 struct udevice *bus, *dev; 129 int ret; 130 131 post_code(0x70); 132 ret = uclass_get_device(UCLASS_PCI, 0, &bus); 133 post_code(0x71); 134 if (ret) 135 return ret; 136 post_code(0x72); 137 hose = dev_get_uclass_priv(bus); 138 139 /* TODO(sjg@chromium.org): Get rid of gd->hose */ 140 gd->hose = hose; 141 142 ret = uclass_first_device(UCLASS_LPC, &dev); 143 if (!dev) 144 return -ENODEV; 145 146 enable_spi_prefetch(hose, PCH_LPC_DEV); 147 148 /* This is already done in start.S, but let's do it in C */ 149 enable_port80_on_lpc(hose, PCH_LPC_DEV); 150 151 set_spi_speed(); 152 153 /* 154 * We should do as little as possible before the serial console is 155 * up. Perhaps this should move to later. Our next lot of init 156 * happens in print_cpuinfo() when we have a console 157 */ 158 ret = set_flex_ratio_to_tdp_nominal(); 159 if (ret) 160 return ret; 161 162 return 0; 163 } 164 165 static int enable_smbus(void) 166 { 167 pci_dev_t dev; 168 uint16_t value; 169 170 /* Set the SMBus device statically. */ 171 dev = PCI_BDF(0x0, 0x1f, 0x3); 172 173 /* Check to make sure we've got the right device. */ 174 value = x86_pci_read_config16(dev, 0x0); 175 if (value != 0x8086) { 176 printf("SMBus controller not found\n"); 177 return -ENOSYS; 178 } 179 180 /* Set SMBus I/O base. */ 181 x86_pci_write_config32(dev, SMB_BASE, 182 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 183 184 /* Set SMBus enable. */ 185 x86_pci_write_config8(dev, HOSTC, HST_EN); 186 187 /* Set SMBus I/O space enable. */ 188 x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 189 190 /* Disable interrupt generation. */ 191 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 192 193 /* Clear any lingering errors, so transactions can run. */ 194 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 195 debug("SMBus controller enabled\n"); 196 197 return 0; 198 } 199 200 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 201 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 202 #define PCH_XHCI_TEMP_BAR0 0xe8001000 203 204 /* 205 * Setup USB controller MMIO BAR to prevent the reference code from 206 * resetting the controller. 207 * 208 * The BAR will be re-assigned during device enumeration so these are only 209 * temporary. 210 * 211 * This is used to speed up the resume path. 212 */ 213 static void enable_usb_bar(void) 214 { 215 pci_dev_t usb0 = PCH_EHCI1_DEV; 216 pci_dev_t usb1 = PCH_EHCI2_DEV; 217 pci_dev_t usb3 = PCH_XHCI_DEV; 218 u32 cmd; 219 220 /* USB Controller 1 */ 221 x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0, 222 PCH_EHCI0_TEMP_BAR0); 223 cmd = x86_pci_read_config32(usb0, PCI_COMMAND); 224 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 225 x86_pci_write_config32(usb0, PCI_COMMAND, cmd); 226 227 /* USB Controller 1 */ 228 x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0, 229 PCH_EHCI1_TEMP_BAR0); 230 cmd = x86_pci_read_config32(usb1, PCI_COMMAND); 231 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 232 x86_pci_write_config32(usb1, PCI_COMMAND, cmd); 233 234 /* USB3 Controller */ 235 x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0, 236 PCH_XHCI_TEMP_BAR0); 237 cmd = x86_pci_read_config32(usb3, PCI_COMMAND); 238 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 239 x86_pci_write_config32(usb3, PCI_COMMAND, cmd); 240 } 241 242 static int report_bist_failure(void) 243 { 244 if (gd->arch.bist != 0) { 245 post_code(POST_BIST_FAILURE); 246 printf("BIST failed: %08x\n", gd->arch.bist); 247 return -EFAULT; 248 } 249 250 return 0; 251 } 252 253 int print_cpuinfo(void) 254 { 255 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 256 char processor_name[CPU_MAX_NAME_LEN]; 257 const char *name; 258 uint32_t pm1_cnt; 259 uint16_t pm1_sts; 260 int ret; 261 262 /* Halt if there was a built in self test failure */ 263 ret = report_bist_failure(); 264 if (ret) 265 return ret; 266 267 enable_lapic(); 268 269 ret = microcode_update_intel(); 270 if (ret) 271 return ret; 272 273 /* Enable upper 128bytes of CMOS */ 274 writel(1 << 2, RCB_REG(RC)); 275 276 /* TODO: cmos_post_init() */ 277 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 278 debug("soft reset detected\n"); 279 boot_mode = PEI_BOOT_SOFT_RESET; 280 281 /* System is not happy after keyboard reset... */ 282 debug("Issuing CF9 warm reset\n"); 283 reset_cpu(0); 284 } 285 286 /* Early chipset init required before RAM init can work */ 287 sandybridge_early_init(SANDYBRIDGE_MOBILE); 288 289 /* Check PM1_STS[15] to see if we are waking from Sx */ 290 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 291 292 /* Read PM1_CNT[12:10] to determine which Sx state */ 293 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 294 295 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 296 debug("Resume from S3 detected, but disabled.\n"); 297 } else { 298 /* 299 * TODO: An indication of life might be possible here (e.g. 300 * keyboard light) 301 */ 302 } 303 post_code(POST_EARLY_INIT); 304 305 /* Enable SPD ROMs and DDR-III DRAM */ 306 ret = enable_smbus(); 307 if (ret) 308 return ret; 309 310 /* Prepare USB controller early in S3 resume */ 311 if (boot_mode == PEI_BOOT_RESUME) 312 enable_usb_bar(); 313 314 gd->arch.pei_boot_mode = boot_mode; 315 316 /* TODO: Move this to the board or driver */ 317 x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); 318 x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); 319 320 /* Print processor name */ 321 name = cpu_get_name(processor_name); 322 printf("CPU: %s\n", name); 323 324 post_code(POST_CPU_INFO); 325 326 return 0; 327 } 328 329 void board_debug_uart_init(void) 330 { 331 /* This enables the debug UART */ 332 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, 333 PCI_SIZE_16); 334 } 335