xref: /rk3399_rockchip-uboot/arch/x86/dts/chromebook_link.dts (revision 12d6929e1f70da7bdbd7ac1de3db33fdff50a716) 
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "keyboard.dtsi"
5/include/ "serial.dtsi"
6/include/ "rtc.dtsi"
7/include/ "tsc_timer.dtsi"
8
9/ {
10	model = "Google Link";
11	compatible = "google,link", "intel,celeron-ivybridge";
12
13	aliases {
14		spi0 = "/pci/pch/spi";
15	};
16
17	config {
18	       silent_console = <0>;
19	};
20
21	gpioa {
22		compatible = "intel,ich6-gpio";
23		u-boot,dm-pre-reloc;
24		reg = <0 0x10>;
25		bank-name = "A";
26	};
27
28	gpiob {
29		compatible = "intel,ich6-gpio";
30		u-boot,dm-pre-reloc;
31		reg = <0x30 0x10>;
32		bank-name = "B";
33	};
34
35	gpioc {
36		compatible = "intel,ich6-gpio";
37		u-boot,dm-pre-reloc;
38		reg = <0x40 0x10>;
39		bank-name = "C";
40	};
41
42	chosen {
43		stdout-path = "/serial";
44	};
45
46	keyboard {
47		intel,duplicate-por;
48	};
49
50	spd {
51		compatible = "memory-spd";
52		#address-cells = <1>;
53		#size-cells = <0>;
54		elpida_4Gb_1600_x16 {
55			reg = <0>;
56			data = [92 10 0b 03 04 19 02 02
57				03 52 01 08 0a 00 fe 00
58				69 78 69 3c 69 11 18 81
59				20 08 3c 3c 01 40 83 81
60				00 00 00 00 00 00 00 00
61				00 00 00 00 00 00 00 00
62				00 00 00 00 00 00 00 00
63				00 00 00 00 0f 11 42 00
64				00 00 00 00 00 00 00 00
65				00 00 00 00 00 00 00 00
66				00 00 00 00 00 00 00 00
67				00 00 00 00 00 00 00 00
68				00 00 00 00 00 00 00 00
69				00 00 00 00 00 00 00 00
70				00 00 00 00 00 02 fe 00
71				11 52 00 00 00 07 7f 37
72				45 42 4a 32 30 55 47 36
73				45 42 55 30 2d 47 4e 2d
74				46 20 30 20 02 fe 00 00
75				00 00 00 00 00 00 00 00
76				00 00 00 00 00 00 00 00
77				00 00 00 00 00 00 00 00
78				00 00 00 00 00 00 00 00
79				00 00 00 00 00 00 00 00
80				00 00 00 00 00 00 00 00
81				00 00 00 00 00 00 00 00
82				00 00 00 00 00 00 00 00
83				00 00 00 00 00 00 00 00
84				00 00 00 00 00 00 00 00
85				00 00 00 00 00 00 00 00
86				00 00 00 00 00 00 00 00
87				00 00 00 00 00 00 00 00];
88		};
89		samsung_4Gb_1600_1.35v_x16 {
90			reg = <1>;
91			data = [92 11 0b 03 04 19 02 02
92				03 11 01 08 0a 00 fe 00
93				69 78 69 3c 69 11 18 81
94				f0 0a 3c 3c 01 40 83 01
95				00 80 00 00 00 00 00 00
96				00 00 00 00 00 00 00 00
97				00 00 00 00 00 00 00 00
98				00 00 00 00 0f 11 02 00
99				00 00 00 00 00 00 00 00
100				00 00 00 00 00 00 00 00
101				00 00 00 00 00 00 00 00
102				00 00 00 00 00 00 00 00
103				00 00 00 00 00 00 00 00
104				00 00 00 00 00 00 00 00
105				00 00 00 00 00 80 ce 01
106				00 00 00 00 00 00 6a 04
107				4d 34 37 31 42 35 36 37
108				34 42 48 30 2d 59 4b 30
109				20 20 00 00 80 ce 00 00
110				00 00 00 00 00 00 00 00
111				00 00 00 00 00 00 00 00
112				00 00 00 00 00 00 00 00
113				00 00 00 00 00 00 00 00
114				00 00 00 00 00 00 00 00
115				00 00 00 00 00 00 00 00
116				00 00 00 00 00 00 00 00
117				00 00 00 00 00 00 00 00
118				00 00 00 00 00 00 00 00
119				00 00 00 00 00 00 00 00
120				00 00 00 00 00 00 00 00
121				00 00 00 00 00 00 00 00
122				00 00 00 00 00 00 00 00];
123			};
124		micron_4Gb_1600_1.35v_x16 {
125			reg = <2>;
126			data = [92 11 0b 03 04 19 02 02
127				03 11 01 08 0a 00 fe 00
128				69 78 69 3c 69 11 18 81
129				20 08 3c 3c 01 40 83 05
130				00 00 00 00 00 00 00 00
131				00 00 00 00 00 00 00 00
132				00 00 00 00 00 00 00 00
133				00 00 00 00 0f 01 02 00
134				00 00 00 00 00 00 00 00
135				00 00 00 00 00 00 00 00
136				00 00 00 00 00 00 00 00
137				00 00 00 00 00 00 00 00
138				00 00 00 00 00 00 00 00
139				00 00 00 00 00 00 00 00
140				00 00 00 00 00 80 2c 00
141				00 00 00 00 00 00 ad 75
142				34 4b 54 46 32 35 36 36
143				34 48 5a 2d 31 47 36 45
144				31 20 45 31 80 2c 00 00
145				00 00 00 00 00 00 00 00
146				00 00 00 00 00 00 00 00
147				00 00 00 00 00 00 00 00
148				ff ff ff ff ff ff ff ff
149				ff ff ff ff ff ff ff ff
150				ff ff ff ff ff ff ff ff
151				ff ff ff ff ff ff ff ff
152				ff ff ff ff ff ff ff ff
153				ff ff ff ff ff ff ff ff
154				ff ff ff ff ff ff ff ff
155				ff ff ff ff ff ff ff ff
156				ff ff ff ff ff ff ff ff
157				ff ff ff ff ff ff ff ff];
158		};
159	};
160
161	pci {
162		compatible = "intel,pci-ivybridge", "pci-x86";
163		#address-cells = <3>;
164		#size-cells = <2>;
165		u-boot,dm-pre-reloc;
166		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
167			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
168			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
169		sata {
170			compatible = "intel,pantherpoint-ahci";
171			intel,sata-mode = "ahci";
172			intel,sata-port-map = <1>;
173			intel,sata-port0-gen3-tx = <0x00880a7f>;
174		};
175
176		gma {
177			compatible = "intel,gma";
178			intel,dp_hotplug = <0 0 0x06>;
179			intel,panel-port-select = <1>;
180			intel,panel-power-cycle-delay = <6>;
181			intel,panel-power-up-delay = <2000>;
182			intel,panel-power-down-delay = <500>;
183			intel,panel-power-backlight-on-delay = <2000>;
184			intel,panel-power-backlight-off-delay = <2000>;
185			intel,cpu-backlight = <0x00000200>;
186			intel,pch-backlight = <0x04000000>;
187		};
188
189		pch@1f,0 {
190			reg = <0x0000f800 0 0 0 0>;
191			compatible = "intel,bd82x6x", "intel,pch9";
192			u-boot,dm-pre-reloc;
193			#address-cells = <1>;
194			#size-cells = <1>;
195			gen-dec = <0x800 0xfc 0x900 0xfc>;
196			intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
197			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
198						0x80 0x80 0x80 0x80>;
199			intel,gpi-routing = <0 0 0 0 0 0 0 2
200						1 0 0 0 0 0 0 0>;
201			/* Enable EC SMI source */
202			intel,alt-gp-smi-enable = <0x0100>;
203
204			spi {
205				#address-cells = <1>;
206				#size-cells = <0>;
207				compatible = "intel,ich-spi";
208				spi-flash@0 {
209					#size-cells = <1>;
210					#address-cells = <1>;
211					reg = <0>;
212					compatible = "winbond,w25q64",
213							"spi-flash";
214					memory-map = <0xff800000 0x00800000>;
215					rw-mrc-cache {
216						label = "rw-mrc-cache";
217						reg = <0x003e0000 0x00010000>;
218					};
219				};
220			};
221
222			lpc {
223				compatible = "intel,bd82x6x-lpc";
224				#address-cells = <1>;
225				#size-cells = <0>;
226				cros-ec@200 {
227					compatible = "google,cros-ec";
228					reg = <0x204 1 0x200 1 0x880 0x80>;
229
230					/*
231					 * Describes the flash memory within
232					 * the EC
233					 */
234					#address-cells = <1>;
235					#size-cells = <1>;
236					flash@8000000 {
237						reg = <0x08000000 0x20000>;
238						erase-value = <0xff>;
239					};
240				};
241			};
242		};
243	};
244
245	tpm {
246		reg = <0xfed40000 0x5000>;
247		compatible = "infineon,slb9635lpc";
248	};
249
250	microcode {
251		update@0 {
252#include "microcode/m12306a9_0000001b.dtsi"
253		};
254	};
255
256};
257