| #
07d77838 |
| 01-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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| #
3612b1ef |
| 30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Select ARCH_MISC_INIT in the platform Kconfig
arch_misc_init() is intended to do architecture-dependent stuff. This is required by each platform.
Signed-off-by: Bin Meng <bmeng.cn@gma
x86: kconfig: Select ARCH_MISC_INIT in the platform Kconfig
arch_misc_init() is intended to do architecture-dependent stuff. This is required by each platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
30b1ecd2 |
| 30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Let board select BOARD_EARLY_INIT_F
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards.
Signed-off-by: Bin Meng <bmeng
x86: kconfig: Let board select BOARD_EARLY_INIT_F
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
76d1d02f |
| 28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init
At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arc
board_f: x86: Use checkcpu() for CPU init
At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice.
Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
6d54868e |
| 23-May-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-x86
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| #
1e2f7b9e |
| 11-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Call board_final_cleanup() in last_stage_init()
At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, V
x86: Call board_final_cleanup() in last_stage_init()
At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
5bc60d5a |
| 28-Aug-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: coreboot: Convert to use more dm drivers
Move to driver model for RTC, USB and ETH on coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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| #
6f43ba70 |
| 07-Jul-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
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| #
5c564226 |
| 03-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethern
x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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| #
f2653e8d |
| 03-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option
x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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| #
65cdd9be |
| 03-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: coreboot: Fix cosmetic issues
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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| #
e72d3443 |
| 13-Feb-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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| #
ab92da9f |
| 26-Jan-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-x86
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| #
069f5481 |
| 20-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| #
5f88ed5c |
| 13-Jan-2015 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-x86
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| #
aff2523f |
| 01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style,
x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded code.
These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit).
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
f4e7e2d1 |
| 01-Dec-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-x86
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| #
65990d56 |
| 15-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence slightly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@
x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence slightly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| #
746667f1 |
| 24-Nov-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-x86
Conflicts: arch/x86/cpu/Makefile
Signed-off-by: Tom Rini <trini@ti.com>
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| #
a49e3c7f |
| 13-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Make show_boot_progress() common
This function can probably be used on all x86 boards, so move it into the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
378a8634 |
| 13-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used.
Signed-
x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
d1cd0459 |
| 13-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment dis
x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| #
8ef07571 |
| 13-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector.
This initia
x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector.
This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
727c1a98 |
| 11-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying.
Signed-off-by: Simon Glass <sjg@chr
x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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