1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/u-boot-x86.h> 11 #include <flash.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <asm/msr.h> 15 #include <asm/cache.h> 16 #include <asm/cpu.h> 17 #include <asm/io.h> 18 #include <asm/arch-coreboot/tables.h> 19 #include <asm/arch-coreboot/sysinfo.h> 20 #include <asm/arch/timestamp.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int arch_cpu_init(void) 25 { 26 int ret = get_coreboot_info(&lib_sysinfo); 27 if (ret != 0) { 28 printf("Failed to parse coreboot tables.\n"); 29 return ret; 30 } 31 32 timestamp_init(); 33 34 return x86_cpu_init_f(); 35 } 36 37 int board_early_init_f(void) 38 { 39 return 0; 40 } 41 42 int board_early_init_r(void) 43 { 44 /* CPU Speed to 100MHz */ 45 gd->cpu_clk = 100000000; 46 47 /* Crystal is 33.000MHz */ 48 gd->bus_clk = 33000000; 49 50 return 0; 51 } 52 53 void show_boot_progress(int val) 54 { 55 #if MIN_PORT80_KCLOCKS_DELAY 56 /* 57 * Scale the time counter reading to avoid using 64 bit arithmetics. 58 * Can't use get_timer() here becuase it could be not yet 59 * initialized or even implemented. 60 */ 61 if (!gd->arch.tsc_prev) { 62 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 63 gd->arch.tsc_prev = 0; 64 } else { 65 uint32_t now; 66 67 do { 68 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 69 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 70 gd->arch.tsc_prev = now; 71 } 72 #endif 73 outb(val, 0x80); 74 } 75 76 int print_cpuinfo(void) 77 { 78 return default_print_cpuinfo(); 79 } 80 81 int last_stage_init(void) 82 { 83 if (gd->flags & GD_FLG_COLD_BOOT) 84 timestamp_add_to_bootstage(); 85 86 return 0; 87 } 88 89 #ifndef CONFIG_SYS_NO_FLASH 90 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 91 { 92 return 0; 93 } 94 #endif 95 96 int board_eth_init(bd_t *bis) 97 { 98 return pci_eth_init(bis); 99 } 100 101 #define MTRR_TYPE_WP 5 102 #define MTRRcap_MSR 0xfe 103 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 104 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 105 106 void board_final_cleanup(void) 107 { 108 /* Un-cache the ROM so the kernel has one 109 * more MTRR available. 110 * 111 * Coreboot should have assigned this to the 112 * top available variable MTRR. 113 */ 114 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 115 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 116 117 /* Make sure this MTRR is the correct Write-Protected type */ 118 if (top_type == MTRR_TYPE_WP) { 119 disable_caches(); 120 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 121 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 122 enable_caches(); 123 } 124 125 /* Issue SMI to Coreboot to lock down ME and registers */ 126 printf("Finalizing Coreboot\n"); 127 outb(0xcb, 0xb2); 128 } 129 130 void panic_puts(const char *str) 131 { 132 NS16550_t port = (NS16550_t)0x3f8; 133 134 NS16550_init(port, 1); 135 while (*str) 136 NS16550_putc(port, *str++); 137 } 138