phy: phy-rockchip-snps-pcie3: Add pcie3_phymode setting

rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four
lanes, add support in dts so that we can customize in dts.

The phy has two

phy: phy-rockchip-snps-pcie3: Add pcie3_phymode setting

rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four
lanes, add support in dts so that we can customize in dts.

The phy has two port and each port has two lane:
pcie30_phy_mode[2:0]
2: aggregation
1: bifurcation for port 1
0: bifurcation for port 0

Change-Id: I0bdf75b8df7c927f8a59ddb7ec3739b3c9f33a49
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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dt-bindings: Sync include/dt-bindings/phy/phy.h from Linux

Add 4 new phy types which are present in Linux kernel.
DP and SGMII types are used on Xilinx ZynqMP devices.

Signed-off-by: Michal Simek <

dt-bindings: Sync include/dt-bindings/phy/phy.h from Linux

Add 4 new phy types which are present in Linux kernel.
DP and SGMII types are used on Xilinx ZynqMP devices.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I2936173a68a0d42a2e403f2edf4a9b7ae2a89676

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rockchip: dts: rk3568: Resync from kernel-4.19

Resync from kernel-4.19:
(2f153f1fa73c arm64: dts: rockchip: rk3568: add thermal-zone for pvtm)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Cha

rockchip: dts: rk3568: Resync from kernel-4.19

Resync from kernel-4.19:
(2f153f1fa73c arm64: dts: rockchip: rk3568: add thermal-zone for pvtm)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I36fdfc366f4d44f3226b6f8b35ee496701fe021e

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