1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK3568_COMMON_H 8 #define __CONFIG_RK3568_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SPL_FRAMEWORK 13 #define CONFIG_SPL_TEXT_BASE 0x00000000 14 #define CONFIG_SPL_MAX_SIZE 0x00038000 15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17 #define CONFIG_SPL_STACK 0x03fe0000 18 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #ifdef CONFIG_SUPPORT_USBPLUG 24 #define CONFIG_SYS_TEXT_BASE 0x00000000 25 #else 26 #define CONFIG_SYS_TEXT_BASE 0x00a00000 27 #endif 28 29 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30 #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32 #define COUNTER_FREQUENCY 24000000 33 34 #define GICD_BASE 0xfd400000 35 #define GICR_BASE 0xfd460000 36 #define GICC_BASE 0xfd800000 37 38 /* secure otp */ 39 #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 40 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 41 #define OTP_ALL_ONES_NUM_BITS 32 42 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 43 #define OTP_SECURE_BOOT_ENABLE_SIZE 2 44 #define OTP_RSA_HASH_ADDR 0x90 45 #define OTP_RSA_HASH_SIZE 32 46 47 /* MMC/SD IP block */ 48 #define CONFIG_BOUNCE_BUFFER 49 50 /* Nand */ 51 #define CONFIG_SYS_MAX_NAND_DEVICE 1 52 #define CONFIG_SYS_NAND_ONFI_DETECTION 53 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 54 #define CONFIG_SYS_NAND_PAGE_COUNT 64 55 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 56 57 #define CONFIG_SUPPORT_EMMC_RPMB 58 59 #define CONFIG_SYS_SDRAM_BASE 0 60 #define SDRAM_MAX_SIZE 0xf0000000 61 #define CONFIG_PREBOOT 62 63 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 64 65 #ifndef CONFIG_SPL_BUILD 66 /* usb mass storage */ 67 #define CONFIG_USB_FUNCTION_MASS_STORAGE 68 #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 69 70 #define ENV_MEM_LAYOUT_SETTINGS \ 71 "scriptaddr=0x00c00000\0" \ 72 "pxefile_addr_r=0x00e00000\0" \ 73 "fdt_addr_r=0x0a100000\0" \ 74 "kernel_addr_no_bl32_r=0x00280000\0" \ 75 "kernel_addr_r=0x00a80000\0" \ 76 "kernel_addr_c=0x04080000\0" \ 77 "ramdisk_addr_r=0x0a200000\0" 78 79 #include <config_distro_bootcmd.h> 80 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 ENV_MEM_LAYOUT_SETTINGS \ 83 "partitions=" PARTS_RKIMG \ 84 ROCKCHIP_DEVICE_SETTINGS \ 85 RKIMG_DET_BOOTDEV \ 86 BOOTENV 87 88 #undef RKIMG_BOOTCOMMAND 89 #define RKIMG_BOOTCOMMAND \ 90 "boot_fit;" \ 91 "boot_android ${devtype} ${devnum};" \ 92 "run distro_bootcmd;" 93 #endif 94 95 /* rockchip ohci host driver */ 96 #define CONFIG_USB_OHCI_NEW 97 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 98 99 #define CONFIG_LIB_HW_RAND 100 101 #endif 102