| f1c64a08 | 29-Jan-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 st
MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| ab0d0026 | 29-Jan-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: handle mips64 relocs in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64.
Sign
MIPS: handle mips64 relocs in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| a39b1cb7 | 29-Jan-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: use asm.h macros in mips32 start.S
Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those diffe
MIPS: use asm.h macros in mips32 start.S
Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64.
The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| 4a5d8898 | 29-Jan-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: unify cache initialization code
The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move
MIPS: unify cache initialization code
The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| 30374f98 | 29-Jan-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: unify cache maintenance functions
Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & m
MIPS: unify cache maintenance functions
Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| e5200238 | 18-Jan-2015 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: add support for pre-relocation malloc
Implement MIPS specific setup of the gd_t structure to support pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified, a memory area will be reser
MIPS: add support for pre-relocation malloc
Implement MIPS specific setup of the gd_t structure to support pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified, a memory area will be reserved after the initial stack area and the gd->malloc_base pointer will be initialized.
After this patch the new driver model can be used on MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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