| 04f3da39 | 14-Feb-2017 |
Kotaro Hayashi <hayashi.kotaro@socionext.com> |
ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoC
If the DRAM clock duty does not meet the allowable tolerance,
it is marked in an efuse register. If the register is fused,
the boot co
ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoC
If the DRAM clock duty does not meet the allowable tolerance,
it is marked in an efuse register. If the register is fused,
the boot code should compensate for the DRAM clock duty error.
Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com>
[masahiro: simplify code, add git-log]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| fada9eaf | 27-Jan-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: clean up UMC init for PXs2 SoC
Just cosmetic changes:
- Rename prefix DMPHY_ to MPHY_ for consistency
- Move UMC parameters below for complete decouple of PHY and UMC
- Remove r
ARM: uniphier: clean up UMC init for PXs2 SoC
Just cosmetic changes:
- Rename prefix DMPHY_ to MPHY_ for consistency
- Move UMC parameters below for complete decouple of PHY and UMC
- Remove redundant whitespaces
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 7d75254b | 19-Dec-2016 |
Kotaro Hayashi <hayashi.kotaro@socionext.com> |
ARM: uniphier: fix delay fixup code in LD11 UMC init
The ddrphy_shift_rof_hws() never writes back the shifted delay value
to the register, which makes this function non-effective.
Signed-off-by: Ko
ARM: uniphier: fix delay fixup code in LD11 UMC init
The ddrphy_shift_rof_hws() never writes back the shifted delay value
to the register, which makes this function non-effective.
Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com>
[masahiro: add git log]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 5f49845e | 27-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: support DDR PHY parameter dump command for LD11
Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC. Otherwise, 16-digits pointer addresses would break
ARM: uniphier: support DDR PHY parameter dump command for LD11
Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC. Otherwise, 16-digits pointer addresses would break
the log format.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| adf55f63 | 27-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: refactor DDR PHY parameter dump command
Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.
Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c
ARM: uniphier: refactor DDR PHY parameter dump command
Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.
Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 6dd34ae4 | 27-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
ma
ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
macros (and I want to re-use as much code as possible). Change
the code in the more flexible form.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| efaa22e4 | 27-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.h
This PHY might be used for other SoCs in the future.
Avoid including the SoC name in the header name.
Signed-off-by: Masahiro Yamada <yam
ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.h
This PHY might be used for other SoCs in the future.
Avoid including the SoC name in the header name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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