1 /* 2 * Copyright (C) 2015-2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <debug_uart.h> 10 #include <spl.h> 11 12 #include "init.h" 13 #include "micro-support-card.h" 14 #include "soc-info.h" 15 16 struct uniphier_spl_initdata { 17 enum uniphier_soc_id soc_id; 18 void (*bcu_init)(const struct uniphier_board_data *bd); 19 void (*early_clk_init)(void); 20 void (*sbc_init)(void); 21 int (*dpll_init)(const struct uniphier_board_data *bd); 22 int (*memconf_init)(const struct uniphier_board_data *bd); 23 void (*dram_clk_init)(void); 24 int (*umc_init)(const struct uniphier_board_data *bd); 25 }; 26 27 static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { 28 #if defined(CONFIG_ARCH_UNIPHIER_SLD3) 29 { 30 .soc_id = SOC_UNIPHIER_SLD3, 31 .bcu_init = uniphier_sld3_bcu_init, 32 .early_clk_init = uniphier_sld3_early_clk_init, 33 .sbc_init = uniphier_sbc_init_admulti, 34 .dpll_init = uniphier_sld3_dpll_init, 35 .memconf_init = uniphier_memconf_3ch_no_disbit_init, 36 .dram_clk_init = uniphier_sld3_dram_clk_init, 37 .umc_init = uniphier_sld3_umc_init, 38 }, 39 #endif 40 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 41 { 42 .soc_id = SOC_UNIPHIER_LD4, 43 .bcu_init = uniphier_ld4_bcu_init, 44 .early_clk_init = uniphier_sld3_early_clk_init, 45 .sbc_init = uniphier_ld4_sbc_init, 46 .dpll_init = uniphier_ld4_dpll_init, 47 .memconf_init = uniphier_memconf_2ch_init, 48 .dram_clk_init = uniphier_sld3_dram_clk_init, 49 .umc_init = uniphier_ld4_umc_init, 50 }, 51 #endif 52 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 53 { 54 .soc_id = SOC_UNIPHIER_PRO4, 55 .early_clk_init = uniphier_sld3_early_clk_init, 56 .sbc_init = uniphier_sbc_init_savepin, 57 .dpll_init = uniphier_pro4_dpll_init, 58 .memconf_init = uniphier_memconf_2ch_init, 59 .dram_clk_init = uniphier_sld3_dram_clk_init, 60 .umc_init = uniphier_pro4_umc_init, 61 }, 62 #endif 63 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 64 { 65 .soc_id = SOC_UNIPHIER_SLD8, 66 .bcu_init = uniphier_ld4_bcu_init, 67 .early_clk_init = uniphier_sld3_early_clk_init, 68 .sbc_init = uniphier_ld4_sbc_init, 69 .dpll_init = uniphier_sld8_dpll_init, 70 .memconf_init = uniphier_memconf_2ch_init, 71 .dram_clk_init = uniphier_sld3_dram_clk_init, 72 .umc_init = uniphier_sld8_umc_init, 73 }, 74 #endif 75 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 76 { 77 .soc_id = SOC_UNIPHIER_PRO5, 78 .early_clk_init = uniphier_sld3_early_clk_init, 79 .sbc_init = uniphier_sbc_init_savepin, 80 .dpll_init = uniphier_pro5_dpll_init, 81 .memconf_init = uniphier_memconf_2ch_init, 82 .dram_clk_init = uniphier_pro5_dram_clk_init, 83 .umc_init = uniphier_pro5_umc_init, 84 }, 85 #endif 86 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 87 { 88 .soc_id = SOC_UNIPHIER_PXS2, 89 .early_clk_init = uniphier_sld3_early_clk_init, 90 .sbc_init = uniphier_pxs2_sbc_init, 91 .dpll_init = uniphier_pxs2_dpll_init, 92 .memconf_init = uniphier_memconf_3ch_init, 93 .dram_clk_init = uniphier_pxs2_dram_clk_init, 94 .umc_init = uniphier_pxs2_umc_init, 95 }, 96 #endif 97 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 98 { 99 .soc_id = SOC_UNIPHIER_LD6B, 100 .early_clk_init = uniphier_sld3_early_clk_init, 101 .sbc_init = uniphier_pxs2_sbc_init, 102 .dpll_init = uniphier_pxs2_dpll_init, 103 .memconf_init = uniphier_memconf_3ch_init, 104 .dram_clk_init = uniphier_pxs2_dram_clk_init, 105 .umc_init = uniphier_pxs2_umc_init, 106 }, 107 #endif 108 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 109 { 110 .soc_id = SOC_UNIPHIER_LD11, 111 .early_clk_init = uniphier_ld11_early_clk_init, 112 .sbc_init = uniphier_ld11_sbc_init, 113 .dpll_init = uniphier_ld11_dpll_init, 114 .memconf_init = uniphier_memconf_2ch_init, 115 .dram_clk_init = uniphier_ld11_dram_clk_init, 116 .umc_init = uniphier_ld11_umc_init, 117 }, 118 #endif 119 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 120 { 121 .soc_id = SOC_UNIPHIER_LD20, 122 .early_clk_init = uniphier_ld11_early_clk_init, 123 .sbc_init = uniphier_ld11_sbc_init, 124 .dpll_init = uniphier_ld20_dpll_init, 125 .memconf_init = uniphier_memconf_3ch_init, 126 .dram_clk_init = uniphier_ld20_dram_clk_init, 127 .umc_init = uniphier_ld20_umc_init, 128 }, 129 #endif 130 }; 131 132 static const struct uniphier_spl_initdata *uniphier_get_spl_initdata( 133 enum uniphier_soc_id soc_id) 134 { 135 int i; 136 137 for (i = 0; i < ARRAY_SIZE(uniphier_spl_initdata); i++) { 138 if (uniphier_spl_initdata[i].soc_id == soc_id) 139 return &uniphier_spl_initdata[i]; 140 } 141 142 return NULL; 143 } 144 145 void spl_board_init(void) 146 { 147 const struct uniphier_board_data *bd; 148 const struct uniphier_spl_initdata *initdata; 149 enum uniphier_soc_id soc_id; 150 int ret; 151 152 #ifdef CONFIG_DEBUG_UART 153 debug_uart_init(); 154 #endif 155 156 bd = uniphier_get_board_param(); 157 if (!bd) 158 hang(); 159 160 soc_id = uniphier_get_soc_type(); 161 initdata = uniphier_get_spl_initdata(soc_id); 162 if (!initdata) 163 hang(); 164 165 if (initdata->bcu_init) 166 initdata->bcu_init(bd); 167 168 initdata->sbc_init(); 169 170 initdata->early_clk_init(); 171 172 support_card_init(); 173 174 led_puts("L0"); 175 176 #ifdef CONFIG_SPL_SERIAL_SUPPORT 177 preloader_console_init(); 178 #endif 179 180 led_puts("L1"); 181 182 ret = initdata->dpll_init(bd); 183 if (ret) { 184 pr_err("failed to init DPLL\n"); 185 hang(); 186 } 187 188 led_puts("L2"); 189 190 ret = initdata->memconf_init(bd); 191 if (ret) { 192 pr_err("failed to init MEMCONF\n"); 193 hang(); 194 } 195 196 led_puts("L3"); 197 198 initdata->dram_clk_init(); 199 200 led_puts("L4"); 201 202 ret = initdata->umc_init(bd); 203 if (ret) { 204 pr_err("failed to init DRAM\n"); 205 hang(); 206 } 207 208 led_puts("L5"); 209 } 210