| c5161eee | 13-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79fa509ffb8ecd8dd2dc216929d6e8289.
Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a work
Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79fa509ffb8ecd8dd2dc216929d6e8289.
Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3")
was a workaround for sLD3. Now the sLD3 SoC support has been removed.
Revert it to allow to simplify the init code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 0aa8b2c3 | 13-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23.
Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug
Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23.
Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug init code
after page table switch") was intended to support lowlevel debug for
sLD3. Now the sLD3 SoC support has been removed.
Revert it to allow to enable lowlevel debug earlier.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| ee9bc77f | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add uniphier_cache_set_active_ways()
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CP
ARM: uniphier: add uniphier_cache_set_active_ways()
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 7382d178 | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Li
ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 95646e1d | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move outer cache register macros to .c file
Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.
Signed-off-by: Masahiro Y
ARM: uniphier: move outer cache register macros to .c file
Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| c21fadfe | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.
Signe
ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 6f579db7 | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: export uniphier_cache_enable/disable functions
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary
ARM: uniphier: export uniphier_cache_enable/disable functions
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| bcc51c15 | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move lowlevel debug init code after page table switch
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it. It will be much easier
ARM: uniphier: move lowlevel debug init code after page table switch
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it. It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 82d075e7 | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: fix ROM boot mode for PH1-sLD3
Commit 4b50369fb535 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table cre
ARM: uniphier: fix ROM boot mode for PH1-sLD3
Commit 4b50369fb535 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.
The idea here is to check the current page table to determine if
it is a straight map table. If not, adjust the outer cache register
base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 0efbbc5c | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.
Signed-off
ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| e731a538 | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). T
ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). The weak
stub avoids the compile error anyway.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 95a1feca | 10-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: support prefetch and touch operations for outer cache
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.
These functions will be used to transfer
ARM: uniphier: support prefetch and touch operations for outer cache
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.
These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|