1 /* 2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* U-Boot - Common settings for UniPhier Family */ 8 9 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 10 #define __CONFIG_UNIPHIER_COMMON_H__ 11 12 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 13 14 #define CONFIG_SMC911X 15 16 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 17 #define CONFIG_SMC911X_BASE 0 18 #define CONFIG_SMC911X_32_BIT 19 20 /*----------------------------------------------------------------------- 21 * MMU and Cache Setting 22 *----------------------------------------------------------------------*/ 23 24 /* Comment out the following to enable L1 cache */ 25 /* #define CONFIG_SYS_ICACHE_OFF */ 26 /* #define CONFIG_SYS_DCACHE_OFF */ 27 28 #define CONFIG_SYS_CACHELINE_SIZE 32 29 30 #define CONFIG_DISPLAY_CPUINFO 31 #define CONFIG_DISPLAY_BOARDINFO 32 #define CONFIG_MISC_INIT_F 33 #define CONFIG_BOARD_EARLY_INIT_F 34 #define CONFIG_BOARD_EARLY_INIT_R 35 #define CONFIG_BOARD_LATE_INIT 36 37 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 38 39 #define CONFIG_TIMESTAMP 40 41 /* FLASH related */ 42 #define CONFIG_MTD_DEVICE 43 44 /* 45 * uncomment the following to disable FLASH related code. 46 */ 47 /* #define CONFIG_SYS_NO_FLASH */ 48 49 #define CONFIG_FLASH_CFI_DRIVER 50 #define CONFIG_SYS_FLASH_CFI 51 52 #define CONFIG_SYS_MAX_FLASH_SECT 256 53 #define CONFIG_SYS_MONITOR_BASE 0 54 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 55 #define CONFIG_SYS_FLASH_BASE 0 56 57 /* 58 * flash_toggle does not work for out supoort card. 59 * We need to use flash_status_poll. 60 */ 61 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 62 63 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 64 65 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 66 67 /* serial console configuration */ 68 #define CONFIG_BAUDRATE 115200 69 70 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 71 #define CONFIG_USE_ARCH_MEMSET 72 #define CONFIG_USE_ARCH_MEMCPY 73 #endif 74 75 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 76 77 #define CONFIG_CMDLINE_EDITING /* add command line history */ 78 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 79 /* Print Buffer Size */ 80 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 81 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 82 /* Boot Argument Buffer Size */ 83 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 84 85 #define CONFIG_CONS_INDEX 1 86 87 /* #define CONFIG_ENV_IS_NOWHERE */ 88 /* #define CONFIG_ENV_IS_IN_NAND */ 89 #define CONFIG_ENV_IS_IN_MMC 90 #define CONFIG_ENV_OFFSET 0x80000 91 #define CONFIG_ENV_SIZE 0x2000 92 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 93 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_SYS_MMC_ENV_PART 1 96 97 #ifdef CONFIG_ARM64 98 #define CPU_RELEASE_ADDR 0x80000000 99 #define COUNTER_FREQUENCY 50000000 100 #define CONFIG_GICV3 101 #define GICD_BASE 0x5fe00000 102 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 103 #define GICR_BASE 0x5fe40000 104 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 105 #define GICR_BASE 0x5fe80000 106 #endif 107 #else 108 /* Time clock 1MHz */ 109 #define CONFIG_SYS_TIMER_RATE 1000000 110 #endif 111 112 113 #define CONFIG_SYS_MAX_NAND_DEVICE 1 114 #define CONFIG_SYS_NAND_MAX_CHIPS 2 115 #define CONFIG_SYS_NAND_ONFI_DETECTION 116 117 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 118 119 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 120 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 121 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 122 #else 123 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 124 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 125 #endif 126 127 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 128 129 #define CONFIG_SYS_NAND_USE_FLASH_BBT 130 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 131 132 /* USB */ 133 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 134 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 135 #define CONFIG_FAT_WRITE 136 #define CONFIG_DOS_PARTITION 137 138 /* SD/MMC */ 139 #define CONFIG_SUPPORT_EMMC_BOOT 140 #define CONFIG_GENERIC_MMC 141 142 /* memtest works on */ 143 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 144 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 145 146 /* 147 * Network Configuration 148 */ 149 #define CONFIG_SERVERIP 192.168.11.1 150 #define CONFIG_IPADDR 192.168.11.10 151 #define CONFIG_GATEWAYIP 192.168.11.1 152 #define CONFIG_NETMASK 255.255.255.0 153 154 #define CONFIG_LOADADDR 0x84000000 155 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 156 157 #define CONFIG_CMDLINE_EDITING /* add command line history */ 158 159 #define CONFIG_BOOTCOMMAND "run $bootmode" 160 161 #define CONFIG_ROOTPATH "/nfs/root/path" 162 #define CONFIG_NFSBOOTCOMMAND \ 163 "setenv bootargs $bootargs root=/dev/nfs rw " \ 164 "nfsroot=$serverip:$rootpath " \ 165 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 166 "run __nfsboot" 167 168 #ifdef CONFIG_FIT 169 #define CONFIG_BOOTFILE "fitImage" 170 #define LINUXBOOT_ENV_SETTINGS \ 171 "fit_addr=0x00100000\0" \ 172 "fit_addr_r=0x84100000\0" \ 173 "fit_size=0x00f00000\0" \ 174 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 175 "bootm $fit_addr\0" \ 176 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 177 "bootm $fit_addr_r\0" \ 178 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 179 "bootm $fit_addr_r\0" \ 180 "__nfsboot=run tftpboot\0" 181 #else 182 #ifdef CONFIG_ARM64 183 #define CONFIG_CMD_BOOTI 184 #define CONFIG_BOOTFILE "Image" 185 #define LINUXBOOT_CMD "booti" 186 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 187 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 188 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 189 #else 190 #define CONFIG_BOOTFILE "zImage" 191 #define LINUXBOOT_CMD "bootz" 192 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 193 #define KERNEL_SIZE "kernel_size=0x00800000\0" 194 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 195 #endif 196 #define LINUXBOOT_ENV_SETTINGS \ 197 "fdt_addr=0x00100000\0" \ 198 "fdt_addr_r=0x84100000\0" \ 199 "fdt_size=0x00008000\0" \ 200 "kernel_addr=0x00200000\0" \ 201 KERNEL_ADDR_R \ 202 KERNEL_SIZE \ 203 RAMDISK_ADDR \ 204 "ramdisk_addr_r=0x84a00000\0" \ 205 "ramdisk_size=0x00600000\0" \ 206 "ramdisk_file=rootfs.cpio.uboot\0" \ 207 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 208 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 209 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 210 "setexpr kernel_size $kernel_size / 4 &&" \ 211 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 212 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 213 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 214 "run boot_common\0" \ 215 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 216 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 217 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 218 "run boot_common\0" \ 219 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 220 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 221 "tftpboot $fdt_addr_r $fdt_file &&" \ 222 "run boot_common\0" \ 223 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 224 "tftpboot $fdt_addr_r $fdt_file &&" \ 225 "setenv ramdisk_addr_r - &&" \ 226 "run boot_common\0" 227 #endif 228 229 #define CONFIG_EXTRA_ENV_SETTINGS \ 230 "netdev=eth0\0" \ 231 "verify=n\0" \ 232 "nor_base=0x42000000\0" \ 233 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 234 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 235 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 236 "tftpboot $tmp_addr u-boot.bin\0" \ 237 "emmcupdate=mmcsetn &&" \ 238 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 239 "tftpboot u-boot-spl.bin &&" \ 240 "mmc write $loadaddr 0 80 &&" \ 241 "tftpboot u-boot.bin &&" \ 242 "mmc write $loadaddr 80 780\0" \ 243 "nandupdate=nand erase 0 0x00100000 &&" \ 244 "tftpboot u-boot-spl.bin &&" \ 245 "nand write $loadaddr 0 0x00010000 &&" \ 246 "tftpboot u-boot.bin &&" \ 247 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 248 LINUXBOOT_ENV_SETTINGS 249 250 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 251 252 #define CONFIG_SYS_SDRAM_BASE 0x80000000 253 #define CONFIG_NR_DRAM_BANKS 2 254 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 255 #define CONFIG_SYS_MEM_TOP_HIDE 64 256 257 #if defined(CONFIG_ARM64) 258 #define CONFIG_SPL_TEXT_BASE 0x30000000 259 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 260 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 261 defined(CONFIG_ARCH_UNIPHIER_SLD8) 262 #define CONFIG_SPL_TEXT_BASE 0x00040000 263 #else 264 #define CONFIG_SPL_TEXT_BASE 0x00100000 265 #endif 266 267 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 268 #define CONFIG_SPL_STACK (0x30014c00) 269 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 270 #define CONFIG_SPL_STACK (0x3001c000) 271 #else 272 #define CONFIG_SPL_STACK (0x00100000) 273 #endif 274 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 275 276 #define CONFIG_PANIC_HANG 277 278 #define CONFIG_SPL_FRAMEWORK 279 #define CONFIG_SPL_SERIAL_SUPPORT 280 #define CONFIG_SPL_NOR_SUPPORT 281 #ifdef CONFIG_ARM64 282 #define CONFIG_SPL_BOARD_LOAD_IMAGE 283 #else 284 #define CONFIG_SPL_NAND_SUPPORT 285 #define CONFIG_SPL_MMC_SUPPORT 286 #endif 287 288 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ 289 #define CONFIG_SPL_LIBGENERIC_SUPPORT 290 291 #define CONFIG_SPL_BOARD_INIT 292 293 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 294 295 /* subtract sizeof(struct image_header) */ 296 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 297 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 298 299 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 300 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 301 #define CONFIG_SPL_MAX_SIZE 0x10000 302 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 303 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 304 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 305 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 306 #endif 307 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 308 309 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 310