Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: Add reset driver support for Arria 10

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.c

arm: socfpga: Add reset driver support for Arria 10

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.t

arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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Merge git://git.denx.de/u-boot-socfpga

Conflicts:
include/configs/axs101.h

Signed-off-by: Tom Rini <trini@konsulko.com>

arm: socfpga: Define NAND reset bit

Define the NAND reset bit and fix the ordering of the macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: reset: FIX address of tstscratch register

The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset

arm: socfpga: reset: FIX address of tstscratch register

The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map

Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>

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Merge git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits sh

arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

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arm: socfpga: reset: Add SDMMC, QSPI and DMA defines

Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.

Signed-off-by: Marek Vasut <marex@denx

arm: socfpga: reset: Add SDMMC, QSPI and DMA defines

Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <

arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function,

arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
man

arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset

arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Add missing reset manager regs

Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.

Signed-off-by: Marek Vasut <marex@denx.de>

ARM: socfpga: move SoC headers to mach-socfpga/include/mach

Move headers to mach-socfpga as well.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>