1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _RESET_MANAGER_H_ 8 #define _RESET_MANAGER_H_ 9 10 void reset_cpu(ulong addr); 11 void reset_deassert_peripherals_handoff(void); 12 13 void socfpga_bridges_reset(int enable); 14 15 void socfpga_emac_reset(int enable); 16 void socfpga_watchdog_reset(void); 17 void socfpga_spim_enable(void); 18 void socfpga_uart0_enable(void); 19 void socfpga_sdram_enable(void); 20 void socfpga_osc1timer_enable(void); 21 22 struct socfpga_reset_manager { 23 u32 status; 24 u32 ctrl; 25 u32 counts; 26 u32 padding1; 27 u32 mpu_mod_reset; 28 u32 per_mod_reset; 29 u32 per2_mod_reset; 30 u32 brg_mod_reset; 31 u32 misc_mod_reset; 32 u32 tstscratch; 33 }; 34 35 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 36 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 37 #else 38 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 39 #endif 40 41 /* 42 * Define a reset identifier, from which a permodrst bank ID 43 * and reset ID can be extracted using the subsequent macros 44 * RSTMGR_RESET() and RSTMGR_BANK(). 45 */ 46 #define RSTMGR_BANK_OFFSET 8 47 #define RSTMGR_BANK_MASK 0x7 48 #define RSTMGR_RESET_OFFSET 0 49 #define RSTMGR_RESET_MASK 0x1f 50 #define RSTMGR_DEFINE(_bank, _offset) \ 51 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 52 53 /* Extract reset ID from the reset identifier. */ 54 #define RSTMGR_RESET(_reset) \ 55 (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 56 57 /* Extract bank ID from the reset identifier. */ 58 #define RSTMGR_BANK(_reset) \ 59 (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 60 61 /* 62 * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 63 * 0 ... mpumodrst 64 * 1 ... permodrst 65 * 2 ... per2modrst 66 * 3 ... brgmodrst 67 * 4 ... miscmodrst 68 */ 69 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 70 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 71 #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 72 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 73 #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 74 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 75 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 76 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 77 78 /* Create a human-readable reference to SoCFPGA reset. */ 79 #define SOCFPGA_RESET(_name) RSTMGR_##_name 80 81 #endif /* _RESET_MANAGER_H_ */ 82