1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 void board_return_to_bootrom(void) 33 { 34 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 35 } 36 37 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 38 }; 39 40 const char *board_spl_was_booted_from(void) 41 { 42 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 43 const char *bootdevice_ofpath = NULL; 44 45 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 46 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 47 48 if (bootdevice_ofpath) 49 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 50 __func__, bootdevice_brom_id, bootdevice_ofpath); 51 else 52 debug("%s: failed to resolve brom_bootdevice_id %x\n", 53 __func__, bootdevice_brom_id); 54 55 return bootdevice_ofpath; 56 } 57 58 u32 spl_boot_device(void) 59 { 60 u32 boot_device = BOOT_DEVICE_MMC1; 61 62 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 63 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 64 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 65 return BOOT_DEVICE_SPI; 66 #endif 67 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 68 return BOOT_DEVICE_BOOTROM; 69 70 return boot_device; 71 } 72 73 u32 spl_boot_mode(const u32 boot_device) 74 { 75 return MMCSD_MODE_RAW; 76 } 77 78 __weak void rockchip_stimer_init(void) 79 { 80 /* If Timer already enabled, don't re-init it */ 81 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 82 if ( reg & 0x1 ) 83 return; 84 #ifndef CONFIG_ARM64 85 asm volatile("mcr p15, 0, %0, c14, c0, 0" 86 : : "r"(COUNTER_FREQUENCY)); 87 #endif 88 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 89 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 90 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 91 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 92 } 93 94 __weak int arch_cpu_init(void) 95 { 96 return 0; 97 } 98 99 __weak int rk_board_init_f(void) 100 { 101 return 0; 102 } 103 104 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 105 void udelay(unsigned long usec) 106 { 107 __udelay(usec); 108 } 109 110 void hang(void) 111 { 112 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 113 for (;;) 114 ; 115 } 116 117 /** 118 * memset - Fill a region of memory with the given value 119 * @s: Pointer to the start of the area. 120 * @c: The byte to fill the area with 121 * @count: The size of the area. 122 * 123 * Do not use memset() to access IO space, use memset_io() instead. 124 */ 125 void *memset(void *s, int c, size_t count) 126 { 127 unsigned long *sl = (unsigned long *)s; 128 char *s8; 129 130 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 131 unsigned long cl = 0; 132 int i; 133 134 /* do it one word at a time (32 bits or 64 bits) while possible */ 135 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 136 for (i = 0; i < sizeof(*sl); i++) { 137 cl <<= 8; 138 cl |= c & 0xff; 139 } 140 while (count >= sizeof(*sl)) { 141 *sl++ = cl; 142 count -= sizeof(*sl); 143 } 144 } 145 #endif /* fill 8 bits at a time */ 146 s8 = (char *)sl; 147 while (count--) 148 *s8++ = c; 149 150 return s; 151 } 152 #endif 153 154 #ifdef CONFIG_SPL_DM_RESET 155 static void brom_download(void) 156 { 157 if (debug_uart_tstc() && debug_uart_getc() == 0x02) { 158 printf("ctrl+b: Bootrom download!\n"); 159 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 160 do_reset(NULL, 0, 0, NULL); 161 } 162 } 163 #endif 164 165 void board_init_f(ulong dummy) 166 { 167 #ifdef CONFIG_SPL_FRAMEWORK 168 int ret; 169 #if !defined(CONFIG_SUPPORT_TPL) 170 struct udevice *dev; 171 #endif 172 #endif 173 gd->flags = dummy; 174 rockchip_stimer_init(); 175 #define EARLY_UART 176 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 177 /* 178 * Debug UART can be used from here if required: 179 * 180 * debug_uart_init(); 181 * printch('a'); 182 * printhex8(0x1234); 183 * printascii("string"); 184 */ 185 if (!gd->serial.using_pre_serial && 186 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 187 debug_uart_init(); 188 printascii("U-Boot SPL board init"); 189 #endif 190 gd->sys_start_tick = get_ticks(); 191 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 192 rockchip_pcie_ep_init(); 193 #endif 194 #ifdef CONFIG_SPL_FRAMEWORK 195 ret = spl_early_init(); 196 if (ret) { 197 printf("spl_early_init() failed: %d\n", ret); 198 hang(); 199 } 200 #if !defined(CONFIG_SUPPORT_TPL) 201 debug("\nspl:init dram\n"); 202 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 203 if (ret) { 204 printf("DRAM init failed: %d\n", ret); 205 return; 206 } 207 #endif 208 preloader_console_init(); 209 #else 210 /* Some SoCs like rk3036 does not use any frame work */ 211 sdram_init(); 212 #endif 213 #ifdef CONFIG_SPL_DM_RESET 214 brom_download(); 215 #endif 216 arch_cpu_init(); 217 rk_board_init_f(); 218 #ifdef CONFIG_SPL_RAM_DEVICE 219 rockchip_pcie_ep_get_firmware(); 220 #endif 221 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 222 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 223 #endif 224 225 } 226 227 #ifdef CONFIG_SPL_LOAD_FIT 228 int board_fit_config_name_match(const char *name) 229 { 230 /* Just empty function now - can't decide what to choose */ 231 debug("%s: %s\n", __func__, name); 232 233 return 0; 234 } 235 #endif 236 237 int board_init_f_boot_flags(void) 238 { 239 int boot_flags = 0; 240 241 #ifdef CONFIG_FPGA_ROCKCHIP 242 arch_fpga_init(); 243 #endif 244 #ifdef CONFIG_PSTORE 245 param_parse_pstore(); 246 #endif 247 /* pre-loader serial */ 248 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 249 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 250 struct tag *t; 251 252 t = atags_get_tag(ATAG_SERIAL); 253 if (t) { 254 gd->serial.using_pre_serial = 1; 255 gd->serial.enable = t->u.serial.enable; 256 gd->serial.baudrate = t->u.serial.baudrate; 257 gd->serial.addr = t->u.serial.addr; 258 gd->serial.id = t->u.serial.id; 259 gd->baudrate = t->u.serial.baudrate; 260 if (!t->u.serial.enable) 261 boot_flags |= GD_FLG_DISABLE_CONSOLE; 262 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 263 t->u.serial.enable, (u32)t->u.serial.addr, 264 t->u.serial.baudrate, t->u.serial.id); 265 } else 266 #endif 267 { 268 gd->baudrate = CONFIG_BAUDRATE; 269 gd->serial.baudrate = CONFIG_BAUDRATE; 270 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 271 } 272 273 /* The highest priority to turn off (override) console */ 274 #if defined(CONFIG_DISABLE_CONSOLE) 275 boot_flags |= GD_FLG_DISABLE_CONSOLE; 276 #endif 277 278 return boot_flags; 279 } 280 281 #ifdef CONFIG_SPL_BOARD_INIT 282 __weak int rk_spl_board_init(void) 283 { 284 return 0; 285 } 286 287 static int setup_led(void) 288 { 289 #ifdef CONFIG_SPL_LED 290 struct udevice *dev; 291 char *led_name; 292 int ret; 293 294 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 295 if (!led_name) 296 return 0; 297 ret = led_get_by_label(led_name, &dev); 298 if (ret) { 299 debug("%s: get=%d\n", __func__, ret); 300 return ret; 301 } 302 ret = led_set_state(dev, LEDST_ON); 303 if (ret) 304 return ret; 305 #endif 306 307 return 0; 308 } 309 310 void spl_board_init(void) 311 { 312 int ret; 313 314 ret = setup_led(); 315 316 if (ret) { 317 debug("LED ret=%d\n", ret); 318 hang(); 319 } 320 321 rk_spl_board_init(); 322 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 323 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 324 #endif 325 return; 326 } 327 #endif 328 329 void spl_perform_fixups(struct spl_image_info *spl_image) 330 { 331 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 332 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 333 #ifdef BUILD_SPL_TAG 334 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 335 #endif 336 #endif 337 return; 338 } 339 340 #ifdef CONFIG_SPL_KERNEL_BOOT 341 static int spl_rockchip_dnl_key_pressed(void) 342 { 343 #if defined(CONFIG_SPL_INPUT) 344 return key_read(KEY_VOLUMEUP); 345 #else 346 return 0; 347 #endif 348 } 349 350 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 351 bool spl_is_low_power(void) 352 { 353 struct udevice *dev; 354 int ret, voltage; 355 356 ret = uclass_get_device(UCLASS_FG, 0, &dev); 357 if (ret) { 358 debug("Get charge display failed, ret=%d\n", ret); 359 return false; 360 } 361 362 voltage = fuel_gauge_get_voltage(dev); 363 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 364 return false; 365 366 return true; 367 } 368 #endif 369 370 void spl_next_stage(struct spl_image_info *spl) 371 { 372 uint32_t reg_boot_mode; 373 374 if (spl_rockchip_dnl_key_pressed()) { 375 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 376 return; 377 } 378 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 379 if (spl_is_low_power()) { 380 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 381 return; 382 } 383 #endif 384 385 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 386 switch (reg_boot_mode) { 387 case BOOT_COLD: 388 case BOOT_PANIC: 389 case BOOT_WATCHDOG: 390 case BOOT_NORMAL: 391 case BOOT_RECOVERY: 392 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 393 break; 394 default: 395 if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG) 396 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 397 else 398 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 399 } 400 } 401 #endif 402 403 #ifdef CONFIG_SPL_KERNEL_BOOT 404 const char *spl_kernel_partition(struct spl_image_info *spl, 405 struct spl_load_info *info) 406 { 407 struct bootloader_message *bmsg = NULL; 408 u32 boot_mode; 409 int ret, cnt; 410 u32 sector = 0; 411 412 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 413 disk_partition_t part_info; 414 415 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 416 if (ret >= 0) 417 sector = part_info.start; 418 #else 419 sector = CONFIG_SPL_MISC_SECTOR; 420 #endif 421 if (sector) { 422 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 423 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 424 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 425 cnt, bmsg); 426 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 427 free(bmsg); 428 return PART_RECOVERY; 429 } else { 430 free(bmsg); 431 } 432 } 433 434 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 435 436 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 437 } 438 #endif 439 440 void spl_hang_reset(void) 441 { 442 printf("# Reset the board to bootrom #\n"); 443 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 444 /* reset is available after dm setup */ 445 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 446 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 447 do_reset(NULL, 0, 0, NULL); 448 } 449 #endif 450 } 451 452 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 453 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 454 { 455 int ret = 0; 456 457 *otp_index = 0; 458 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 459 struct udevice *dev; 460 u32 index, i, otp_version; 461 u32 bit_count; 462 463 dev = misc_otp_get_device(OTP_S); 464 if (!dev) 465 return -ENODEV; 466 467 otp_version = 0; 468 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 469 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 470 &index, 471 4)) { 472 printf("Can't read rollback index\n"); 473 return -EIO; 474 } 475 476 bit_count = fls(index); 477 otp_version += bit_count; 478 } 479 *otp_index = otp_version; 480 #endif 481 482 return ret; 483 } 484 485 static int fit_write_otp_rollback_index(u32 fit_index) 486 { 487 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 488 struct udevice *dev; 489 u32 index, i, otp_index; 490 491 if (!fit_index) 492 return 0; 493 494 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 495 return -EINVAL; 496 497 dev = misc_otp_get_device(OTP_S); 498 if (!dev) 499 return -ENODEV; 500 501 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 502 return -EIO; 503 504 if (otp_index < fit_index) { 505 /* Write new SW version to otp */ 506 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 507 /* 508 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 509 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 510 * actually be "0xffffffff >> 0". 511 */ 512 if (!fit_index) 513 break; 514 /* convert to base-1 representation */ 515 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 516 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 517 fit_index -= min(fit_index, 518 (u32)OTP_ALL_ONES_NUM_BITS); 519 if (index) { 520 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 521 &index, 522 4)) { 523 printf("Can't write rollback index\n"); 524 return -EIO; 525 } 526 } 527 } 528 } 529 #endif 530 531 return 0; 532 } 533 #endif 534 535 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 536 { 537 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 538 int ret; 539 540 ret = fit_write_otp_rollback_index(gd->rollback_index); 541 if (ret) { 542 panic("Failed to write fit rollback index %d, ret=%d", 543 gd->rollback_index, ret); 544 } 545 #endif 546 547 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 548 misc_decompress_cleanup(); 549 #endif 550 return 0; 551 } 552