arm: adjust PC displayed in exception handlers to point to the failing instruction

Adjust the program counter register to point to the failing
instruction depending on the exeption type.
This makes

arm: adjust PC displayed in exception handlers to point to the failing instruction

Adjust the program counter register to point to the failing
instruction depending on the exeption type.
This makes it easier to localize the offending instruction leading to
a fatal exception.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>

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ARM: remove bogus cp_delay() function

The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr

ARM: remove bogus cp_delay() function

The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr() being optimised out eventually.
This has been fixed in commit 53fd4b8c22bb ("arm: mmu: Add missing volatile for reading SCTLR register")
but the bogus cp_delay() function which was introduced as a workaround
for the malfunctioning get_cr() was never removed.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>

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Merge git://git.denx.de/u-boot-dm

armv7m: Disable D-cache when booting nommu(ARMv7M) Linux kernel

Disable D-Cache is required when booting nommu Linux kernel.
(please see Linux kernel source "arch/arm/kernel/head-nommu.S")

U-Boot i

armv7m: Disable D-cache when booting nommu(ARMv7M) Linux kernel

Disable D-Cache is required when booting nommu Linux kernel.
(please see Linux kernel source "arch/arm/kernel/head-nommu.S")

U-Boot is enabled D-cache and I-Cache at startup.
However, it does not disable D-Cache before
booting nommu Linux kernel.
Therefore, I call dcache_disable()
when the CPU is ARMv7M to fix this problem.

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>

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arm: Disable LPAE if not enabled

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does e

arm: Disable LPAE if not enabled

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
ha

arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: Rename HCTR to HTCR

This appears to be a typo. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>

arm: Add Kconfig symbols used for Linux asm compatibility

Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M a

arm: Add Kconfig symbols used for Linux asm compatibility

Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M always select them.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

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arm: Add declarations to avoid needing to include headers

At present common.h includes various ARM-specific headers. In preparation
for dropping this, add a few explicit declarations.

Signed-off-by

arm: Add declarations to avoid needing to include headers

At present common.h includes various ARM-specific headers. In preparation
for dropping this, add a few explicit declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: Add explicit include of <asm/mach-types.h>

Rather than relying on common.h to provide this include, which is going
away at some point, include it explicitly in each file.

Signed-off-by: Simon

arm: Add explicit include of <asm/mach-types.h>

Rather than relying on common.h to provide this include, which is going
away at some point, include it explicitly in each file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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dm: Use dm.h header when driver mode is used

This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present

S

dm: Use dm.h header when driver mode is used

This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present

Signed-off-by: Simon Glass <sjg@chromium.org>

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armv8: fsl: move ccn504 code into FSL Makefile

The generic ARMv8 assembly code contains routines for setting up
a CCN interconnect, though the Freescale SoCs are the only user.
Link this code only f

armv8: fsl: move ccn504 code into FSL Makefile

The generic ARMv8 assembly code contains routines for setting up
a CCN interconnect, though the Freescale SoCs are the only user.
Link this code only for Freescale targets, this saves some precious
bytes in the chronically tight SPL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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armv8: SPL: only compile GIC code if needed

Not every SoC needs to set up the GIC interrupt controller, so link
think code only when the respective config option is set.
This shaves off some bytes f

armv8: SPL: only compile GIC code if needed

Not every SoC needs to set up the GIC interrupt controller, so link
think code only when the respective config option is set.
This shaves off some bytes from the SPL code size.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spl: fdt: support for fdt fixup for falcon boot

Adding support for fdt fixup to update the
memory node in device tree for falcon boot.

This is needed for single stage or falcon
bootmode, to pass me

spl: fdt: support for fdt fixup for falcon boot

Adding support for fdt fixup to update the
memory node in device tree for falcon boot.

This is needed for single stage or falcon
bootmode, to pass memory configuration to
kernel through DT memory node.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

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spl: make image arg or fdt blob address reconfigurable

At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
dif

spl: make image arg or fdt blob address reconfigurable

At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

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