| a19b0dd6 | 30-May-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c |
| 20583d04 | 17-May-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: support SKU 7 of Tegra20
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20.
My Whistler board has a SoC with this SKU.
Signed-off-by: Stephen Warren
ARM: tegra: support SKU 7 of Tegra20
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20.
My Whistler board has a SoC with this SKU.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 840167c2 | 17-May-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: support SKU 1 of Tegra114
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114.
This value is used on (at least some) Dalmore boards with a production
ARM: tegra: support SKU 1 of Tegra114
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114.
This value is used on (at least some) Dalmore boards with a production rather than engineering chip. Such boards are in the hands of some partners who want to use upstream U-Boot.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 3225f34e | 12-May-2013 |
Bo Shen <voice.shen@atmel.com> |
ARM: atmel: add sama5d3xek support
Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD
ARM: atmel: add sama5d3xek support
Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD card support - LCD support - EMAC support - USB OHCI support
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| 284403aa | 12-May-2013 |
Bo Shen <voice.shen@atmel.com> |
ARM: at91: add Atmel sama5d3 SoC new pmc register
Add Atmel sama5d3 SoC new pmc register
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> |
| c19d13b0 | 08-May-2013 |
Simon Glass <sjg@chromium.org> |
arm: Refactor bootm to reduce #ifdefs
With fewer #ifdefs the code is more readable and more of the code is compiled for all boards. Add defines in the header file to control what features are enable
arm: Refactor bootm to reduce #ifdefs
With fewer #ifdefs the code is more readable and more of the code is compiled for all boards. Add defines in the header file to control what features are enabled, and then use if() instead of #ifdef.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 9e336903 | 16-Apr-2013 |
Wu, Josh <Josh.wu@atmel.com> |
arm: at91: add at91sam9n12ek board support
Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support
Signed-off
arm: at91: add at91sam9n12ek board support
Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support
Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| e542377a | 16-Apr-2013 |
Wu, Josh <Josh.wu@atmel.com> |
arm: at91: add at91sam9n12 register definition
Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12 definitions in at91sam9x5 head file.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Si
arm: at91: add at91sam9n12 register definition
Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12 definitions in at91sam9x5 head file.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| cac423a7 | 11-May-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' |
| ec7023db | 11-May-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h |
| e825b100 | 10-May-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' |
| 4a0eb757 | 24-Apr-2013 |
SRICHARAN R <r.sricharan@ti.com> |
ARM: OMAP: Cleanup boot parameters usage
The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'g
ARM: OMAP: Cleanup boot parameters usage
The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead.
Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
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| fda06812 | 24-Apr-2013 |
SRICHARAN R <r.sricharan@ti.com> |
ARM: OMAP: Correct save_boot_params and replace with 'C' function
Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently
ARM: OMAP: Correct save_boot_params and replace with 'C' function
Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
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| f92f2277 | 24-Apr-2013 |
SRICHARAN R <r.sricharan@ti.com> |
ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow.
Signed-off-by: Sricharan R
ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
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| 76db5b8f | 24-Apr-2013 |
SRICHARAN R <r.sricharan@ti.com> |
ARM: OMAP: Make omap_boot_parameters common across socs
omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs.
Signed-off-by: Sricharan R <r.
ARM: OMAP: Make omap_boot_parameters common across socs
omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
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| 34fa0706 | 22-Apr-2013 |
Eric Benard <eric@eukrea.com> |
davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs
davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h
It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them.
Signed-off-by: Eric Bénard <eric@eukrea.com>
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| 81ac7e51 | 22-Apr-2013 |
Eric Benard <eric@eukrea.com> |
da850: provide davinci_enable_uart0
this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it).
Signed-off-
da850: provide davinci_enable_uart0
this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it).
Signed-off-by: Eric Bénard <eric@eukrea.com>
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| 0b1b60c7 | 17-Apr-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should b
ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state.
There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed.
In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
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| cc175e63 | 04-Apr-2013 |
Enric Balletbo i Serra <eballetbo@iseebcn.com> |
Add DDR3 support for IGEP COM AQUILA/CYGNUS.
These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> |
| 2335b653 | 08-Apr-2013 |
Lubomir Popov <lpopov@mm-sol.com> |
OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has t
OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here.
Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch).
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
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| aebe7ff2 | 08-Apr-2013 |
Lubomir Popov <lpopov@mm-sol.com> |
OMAP5: I2C: Add I2C4 and I2C5 bases
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here.
Signed-off-by: Lubomir
OMAP5: I2C: Add I2C4 and I2C5 bases
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
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| 035d5639 | 20-Mar-2013 |
Matt Porter <mporter@ti.com> |
am33xx: add pll and clock support for TI814x CPSW
Enables required PLLs and clocks for CPSW on TI814x.
Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
| 38e8ce41 | 28-Apr-2013 |
Marek Vasut <marex@denx.de> |
arm: mxs: Add LCDIF registers for i.MX233
Extend the regs-lcdif.h with registers for i.MX233.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio S
arm: mxs: Add LCDIF registers for i.MX233
Extend the regs-lcdif.h with registers for i.MX233.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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| 7411cdf0 | 28-Apr-2013 |
Marek Vasut <marex@denx.de> |
arm: mxs: Add LCDIF clock configuration function
This function turns on the LCDIF clock and configures it's frequency. The dividers settings are calculated within the function and the current implem
arm: mxs: Add LCDIF clock configuration function
This function turns on the LCDIF clock and configures it's frequency. The dividers settings are calculated within the function and the current implementation should be fast and accurate.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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| d5dae85f | 22-Apr-2013 |
Michal Simek <michal.simek@xilinx.com> |
fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by
fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams.
The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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