tegra: add proto for pin_mux_mmc

while at it, fix a typo

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

arm: vectors: provide protypes from vectors.S

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

omap3: board: add missing include and proto

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

arch-mx: add missing include

mxs_wait_mask_set and friends need a declaration
of struct mxs_register_32.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

sunxi: Add clock_get_pll5p() function

This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Camp

sunxi: Add clock_get_pll5p() function

This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Add support for using R_UART as console

The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a

ARM: sunxi: Add support for using R_UART as console

The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Allow specifying module in prcm apb0 init function

The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be re

ARM: sunxi: Allow specifying module in prcm apb0 init function

The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Add support for R_PIO gpio banks

The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.

Also add a clear description a

ARM: sunxi: Add support for R_PIO gpio banks

The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.

Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Add basic A23 support

The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do no

ARM: sunxi: Add basic A23 support

The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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mmc: sunxi: Add support for sun8i (A23)

The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by: Chen-

mmc: sunxi: Add support for sun8i (A23)

The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Add sun8i (A23) UART0 pin mux support

UART0 pin muxes on the A23 have a different function value.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

ARM: sunxi: Fix reset command on sun6i/sun8i

The watchdog on sun6i/sun8i has a different layout.

Add the new layout and fix up the setup functions so that reset works.

Signed-off-by: Chen-Yu Tsai

ARM: sunxi: Fix reset command on sun6i/sun8i

The watchdog on sun6i/sun8i has a different layout.

Add the new layout and fix up the setup functions so that reset works.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]

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ARM: sunxi: Add sun6i/sun8i timer block register definition

The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.

Also note that th

ARM: sunxi: Add sun6i/sun8i timer block register definition

The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.

Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sunxi: Move watchdog register definitions to separate file

On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
lin

ARM: sunxi: Move watchdog register definitions to separate file

On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.

Move the register definitions to a separate file to facilitate
supporting newer SoCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi: Use PG3 - PG8 as io-pins for mmc1

None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of m

sunxi: Use PG3 - PG8 as io-pins for mmc1

None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi: When we've both mmc0 and mmc2, detect from which one we're booting

sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a si

sunxi: When we've both mmc0 and mmc2, detect from which one we're booting

sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.

When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sun6i: Define UART0 pins for A31

UART0 is the default debug/console UART on the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

ARM: sunxi-mmc: Add mmc support for sun6i / A31

The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by:

ARM: sunxi-mmc: Add mmc support for sun6i / A31

The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sun6i: Add clock support

This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has

ARM: sun6i: Add clock support

This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sun6i: Add support for the power reset control module found on the A31

The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block

ARM: sun6i: Add support for the power reset control module found on the A31

The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: sun6i: Add base address for the new controllers in A31

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by:

ARM: sun6i: Add base address for the new controllers in A31

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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dm: serial: use Driver Model for UniPhier serial driver

This commit converts UniPhier on-chip serial driver to driver model.

Since UniPhier SoCs do not have Device Tree support, some board files
sh

dm: serial: use Driver Model for UniPhier serial driver

This commit converts UniPhier on-chip serial driver to driver model.

Since UniPhier SoCs do not have Device Tree support, some board files
should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories.
(Device Tree support for UniPhier platform is still under way.)

Now the base address and master clock frequency are passed from
platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and
CONFIG_SYS_UNIPHIER_UART_CLK should be removed.

Tested on UniPhier PH1-LD4 ref board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>

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dm: omap: gpio: Support driver model

Add driver model support to this driver, while retaining support for the
legacy system. Driver model GPIO support is enabled with CONFIG_DM_GPIO
as usual.

Since

dm: omap: gpio: Support driver model

Add driver model support to this driver, while retaining support for the
legacy system. Driver model GPIO support is enabled with CONFIG_DM_GPIO
as usual.

Since gpio_is_valid() no longer exists, we can use the -EINVAL error
returned from gpio_request().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>

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Merge branch 'master' of git://git.denx.de/u-boot-tegra

omap3/am33xx: mux: fix several checkpatch issues

Fix the following checkpatch issues:

CHECK: No space is necessary after a cast
\#39: FILE: arch/arm/include/asm/arch-am33xx/mux.h:39:
+#define PAD_C

omap3/am33xx: mux: fix several checkpatch issues

Fix the following checkpatch issues:

CHECK: No space is necessary after a cast
\#39: FILE: arch/arm/include/asm/arch-am33xx/mux.h:39:
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \

CHECK: Avoid CamelCase: <CONTROL_PADCONF_JTAG_nTRST>
\#284: FILE: arch/arm/include/asm/arch-omap3/mux.h:284:
+#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C

ERROR: space required after that ',' (ctx:VxV)
\#446: FILE: arch/arm/include/asm/arch-omap3/mux.h:446:
+#define MUX_VAL(OFFSET,VALUE)\
^
Cc: Raphael Assenat <raph@8d.com>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefan Roese <sr@denx.de>

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