| a7b1808e | 01-Jun-2015 |
Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> |
colibri_vf: Add pinmux entries for GPIOs
Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.
Acked-by: Stef
colibri_vf: Add pinmux entries for GPIOs
Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.
Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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| e7b860fa | 15-Apr-2015 |
Sanchayan Maity <maitysanchayan@gmail.com> |
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC.
- CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC.
- CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
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| 1db503c4 | 15-Apr-2015 |
Sanchayan Maity <maitysanchayan@gmail.com> |
ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows use of variable ${soc} for Li
ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows use of variable ${soc} for Linux device tree files. Detect VF5xx CPU's by reading the CPU count register. We can determine the second number of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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| 6c81a93d | 11-Mar-2014 |
Marcel Ziswiler <marcel@ziswiler.com> |
arm: vf610: add enet1 support
This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secon
arm: vf610: add enet1 support
This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
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| c7098965 | 11-Mar-2014 |
Marcel Ziswiler <marcel@ziswiler.com> |
arm: vf610: add uart0 clock/iomux definitions
Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux definitions for UART0 (aka. SCI0).
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.c
arm: vf610: add uart0 clock/iomux definitions
Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux definitions for UART0 (aka. SCI0).
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
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