xref: /rk3399_rockchip-uboot/include/configs/trats.h (revision c19a8bc5711ec63e905ef91f045a1489f0aa3cb0)
1 /*
2  * Copyright (C) 2011 Samsung Electronics
3  * Heungjun Kim <riverful.kim@samsung.com>
4  *
5  * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_TRATS_H
11 #define __CONFIG_TRATS_H
12 
13 #include <configs/exynos4-dt.h>
14 
15 #define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */
16 
17 #define CONFIG_TRATS
18 
19 
20 #define CONFIG_TIZEN			/* TIZEN lib */
21 
22 #define CONFIG_SYS_L2CACHE_OFF
23 #ifndef CONFIG_SYS_L2CACHE_OFF
24 #define CONFIG_SYS_L2_PL310
25 #define CONFIG_SYS_PL310_BASE	0x10502000
26 #endif
27 
28 /* TRATS has 4 banks of DRAM */
29 #define CONFIG_NR_DRAM_BANKS		4
30 #define CONFIG_SYS_SDRAM_BASE		0x40000000
31 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
32 #define CONFIG_SYS_TEXT_BASE		0x63300000
33 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
34 
35 /* memtest works on */
36 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
37 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
38 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
39 
40 #define CONFIG_SYS_TEXT_BASE		0x63300000
41 
42 #include <linux/sizes.h>
43 /* Size of malloc() pool */
44 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
45 
46 /* select serial console configuration */
47 #define CONFIG_SERIAL2
48 #define CONFIG_BAUDRATE			115200
49 
50 /* Console configuration */
51 #define CONFIG_SYS_CONSOLE_INFO_QUIET
52 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
53 
54 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */
55 #define MACH_TYPE_TRATS			3928
56 #define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
57 
58 #define CONFIG_BOOTARGS			"Please use defined boot"
59 #define CONFIG_BOOTCOMMAND		"run mmcboot"
60 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
61 
62 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
63 					- GENERATED_GBL_DATA_SIZE)
64 
65 #define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
66 
67 #define CONFIG_SYS_MONITOR_BASE	0x00000000
68 
69 #define CONFIG_BOOTBLOCK		"10"
70 #define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
71 
72 #define CONFIG_ENV_IS_IN_MMC
73 #define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
74 #define CONFIG_ENV_SIZE			4096
75 #define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
76 
77 #define CONFIG_ENV_OVERWRITE
78 
79 #define CONFIG_ENV_VARS_UBOOT_CONFIG
80 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
81 
82 /* Tizen - partitions definitions */
83 #define PARTS_CSA		"csa-mmc"
84 #define PARTS_BOOT		"boot"
85 #define PARTS_QBOOT		"qboot"
86 #define PARTS_CSC		"csc"
87 #define PARTS_ROOT		"platform"
88 #define PARTS_DATA		"data"
89 #define PARTS_UMS		"ums"
90 
91 #define PARTS_DEFAULT \
92 	"uuid_disk=${uuid_gpt_disk};" \
93 	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
94 	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
95 	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
96 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
97 	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
98 	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
99 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
100 
101 #define CONFIG_DFU_ALT \
102 	"u-boot raw 0x80 0x400;" \
103 	"/uImage ext4 0 2;" \
104 	"/modem.bin ext4 0 2;" \
105 	"/exynos4210-trats.dtb ext4 0 2;" \
106 	""PARTS_CSA" part 0 1;" \
107 	""PARTS_BOOT" part 0 2;" \
108 	""PARTS_QBOOT" part 0 3;" \
109 	""PARTS_CSC" part 0 4;" \
110 	""PARTS_ROOT" part 0 5;" \
111 	""PARTS_DATA" part 0 6;" \
112 	""PARTS_UMS" part 0 7;" \
113 	"params.bin raw 0x38 0x8\0"
114 
115 #define CONFIG_EXTRA_ENV_SETTINGS \
116 	"bootk=" \
117 		"run loaduimage;" \
118 		"if run loaddtb; then " \
119 			"bootm 0x40007FC0 - ${fdtaddr};" \
120 		"fi;" \
121 		"bootm 0x40007FC0;\0" \
122 	"updatebackup=" \
123 		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
124 		"mmc dev 0 0\0" \
125 	"updatebootb=" \
126 		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
127 	"lpj=lpj=3981312\0" \
128 	"nfsboot=" \
129 		"setenv bootargs root=/dev/nfs rw " \
130 		"nfsroot=${nfsroot},nolock,tcp " \
131 		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
132 		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
133 		"; run bootk\0" \
134 	"ramfsboot=" \
135 		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
136 		"${console} ${meminfo} " \
137 		"initrd=0x43000000,8M ramdisk=8192\0" \
138 	"mmcboot=" \
139 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
140 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
141 		"run bootk\0" \
142 	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
143 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
144 	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
145 	"verify=n\0" \
146 	"rootfstype=ext4\0" \
147 	"console=" CONFIG_DEFAULT_CONSOLE \
148 	"meminfo=crashkernel=32M@0x50000000\0" \
149 	"nfsroot=/nfsroot/arm\0" \
150 	"bootblock=" CONFIG_BOOTBLOCK "\0" \
151 	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
152 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
153 		"${fdtfile}\0" \
154 	"mmcdev=0\0" \
155 	"mmcbootpart=2\0" \
156 	"mmcrootpart=5\0" \
157 	"opts=always_resume=1\0" \
158 	"partitions=" PARTS_DEFAULT \
159 	"dfu_alt_info=" CONFIG_DFU_ALT \
160 	"spladdr=0x40000100\0" \
161 	"splsize=0x200\0" \
162 	"splfile=falcon.bin\0" \
163 	"spl_export=" \
164 		   "setexpr spl_imgsize ${splsize} + 8 ;" \
165 		   "setenv spl_imgsize 0x${spl_imgsize};" \
166 		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
167 		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
168 		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
169 		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
170 		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
171 		   "spl export atags 0x40007FC0;" \
172 		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
173 		   "mw.l ${spl_addr_tmp} ${splsize};" \
174 		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
175 		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
176 		   "setenv spl_imgsize;" \
177 		   "setenv spl_imgaddr;" \
178 		   "setenv spl_addr_tmp;\0" \
179 	"fdtaddr=40800000\0" \
180 
181 /* Falcon mode definitions */
182 #define CONFIG_CMD_SPL
183 #define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
184 
185 /* GPT */
186 #define CONFIG_RANDOM_UUID
187 
188 /* I2C */
189 #include <asm/arch/gpio.h>
190 
191 #define CONFIG_CMD_I2C
192 
193 #define CONFIG_SYS_I2C
194 #define CONFIG_SYS_I2C_S3C24X0
195 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
196 #define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
197 #define CONFIG_MAX_I2C_NUM		8
198 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
199 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
200 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
201 #define CONFIG_SOFT_I2C_READ_REPEATED_START
202 #define CONFIG_SYS_I2C_INIT_BOARD
203 
204 /* I2C FG */
205 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
206 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
207 
208 /* POWER */
209 #define CONFIG_POWER
210 #define CONFIG_POWER_I2C
211 #define CONFIG_POWER_MAX8997
212 
213 #define CONFIG_POWER_FG
214 #define CONFIG_POWER_FG_MAX17042
215 #define CONFIG_POWER_MUIC
216 #define CONFIG_POWER_MUIC_MAX8997
217 #define CONFIG_POWER_BATTERY
218 #define CONFIG_POWER_BATTERY_TRATS
219 
220 /* Security subsystem - enable hw_rand() */
221 #define CONFIG_EXYNOS_ACE_SHA
222 #define CONFIG_LIB_HW_RAND
223 
224 /* Common misc for Samsung */
225 #define CONFIG_MISC_COMMON
226 
227 #define CONFIG_MISC_INIT_R
228 
229 /* Download menu - Samsung common */
230 #define CONFIG_LCD_MENU
231 #define CONFIG_LCD_MENU_BOARD
232 
233 /* Download menu - definitions for check keys */
234 #ifndef __ASSEMBLY__
235 #include <power/max8997_pmic.h>
236 
237 #define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
238 #define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
239 #define KEY_PWR_STATUS_MASK		(1 << 0)
240 #define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
241 #define KEY_PWR_INTERRUPT_MASK		(1 << 0)
242 
243 #define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
244 #define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
245 #endif /* __ASSEMBLY__ */
246 
247 /* LCD console */
248 #define LCD_BPP			LCD_COLOR16
249 #define CONFIG_SYS_WHITE_ON_BLACK
250 
251 /* LCD */
252 #define CONFIG_EXYNOS_FB
253 #define CONFIG_LCD
254 #define CONFIG_CMD_BMP
255 #define CONFIG_BMP_16BPP
256 #define CONFIG_FB_ADDR		0x52504000
257 #define CONFIG_S6E8AX0
258 #define CONFIG_EXYNOS_MIPI_DSIM
259 #define CONFIG_VIDEO_BMP_GZIP
260 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
261 
262 #endif	/* __CONFIG_H */
263