1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3128_H 8 #define _ASM_ARCH_CRU_RK3128_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (594 * MHz) 17 18 #define CORE_PERI_HZ 150000000 19 #define CORE_ACLK_HZ 300000000 20 21 #define BUS_ACLK_HZ 148500000 22 #define BUS_HCLK_HZ 148500000 23 #define BUS_PCLK_HZ 74250000 24 25 #define PERI_ACLK_HZ 148500000 26 #define PERI_HCLK_HZ 148500000 27 #define PERI_PCLK_HZ 74250000 28 29 /* Private data for the clock driver - used by rockchip_get_cru() */ 30 struct rk3128_clk_priv { 31 struct rk3128_cru *cru; 32 ulong rate; 33 }; 34 35 struct rk3128_cru { 36 struct rk3128_pll { 37 unsigned int con0; 38 unsigned int con1; 39 unsigned int con2; 40 unsigned int con3; 41 } pll[4]; 42 unsigned int cru_mode_con; 43 unsigned int cru_clksel_con[35]; 44 unsigned int cru_clkgate_con[11]; 45 unsigned int reserved; 46 unsigned int cru_glb_srst_fst_value; 47 unsigned int cru_glb_srst_snd_value; 48 unsigned int reserved1[2]; 49 unsigned int cru_softrst_con[9]; 50 unsigned int cru_misc_con; 51 unsigned int reserved2[2]; 52 unsigned int cru_glb_cnt_th; 53 unsigned int reserved3[3]; 54 unsigned int cru_glb_rst_st; 55 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 56 unsigned int cru_sdmmc_con[2]; 57 unsigned int cru_sdio_con[2]; 58 unsigned int reserved5[2]; 59 unsigned int cru_emmc_con[2]; 60 unsigned int reserved6[4]; 61 unsigned int cru_pll_prg_en; 62 }; 63 check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 64 65 struct pll_div { 66 u32 refdiv; 67 u32 fbdiv; 68 u32 postdiv1; 69 u32 postdiv2; 70 u32 frac; 71 }; 72 73 enum { 74 /* PLLCON0*/ 75 PLL_POSTDIV1_SHIFT = 12, 76 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 77 PLL_FBDIV_SHIFT = 0, 78 PLL_FBDIV_MASK = 0xfff, 79 80 /* PLLCON1 */ 81 PLL_RST_SHIFT = 14, 82 PLL_PD_SHIFT = 13, 83 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 84 PLL_DSMPD_SHIFT = 12, 85 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 86 PLL_LOCK_STATUS_SHIFT = 10, 87 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 88 PLL_POSTDIV2_SHIFT = 6, 89 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 90 PLL_REFDIV_SHIFT = 0, 91 PLL_REFDIV_MASK = 0x3f, 92 93 /* CRU_MODE */ 94 GPLL_MODE_SHIFT = 12, 95 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 96 GPLL_MODE_SLOW = 0, 97 GPLL_MODE_NORM, 98 GPLL_MODE_DEEP, 99 DPLL_MODE_SHIFT = 4, 100 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 101 DPLL_MODE_SLOW = 0, 102 DPLL_MODE_NORM, 103 APLL_MODE_SHIFT = 0, 104 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 105 APLL_MODE_SLOW = 0, 106 APLL_MODE_NORM, 107 108 /* CRU_CLK_SEL0_CON */ 109 BUS_ACLK_PLL_SEL_SHIFT = 14, 110 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 111 BUS_ACLK_PLL_SEL_CPLL = 0, 112 BUS_ACLK_PLL_SEL_GPLL, 113 BUS_ACLK_PLL_SEL_GPLL_DIV2, 114 BUS_ACLK_PLL_SEL_GPLL_DIV3, 115 BUS_ACLK_DIV_SHIFT = 8, 116 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 117 CORE_CLK_PLL_SEL_SHIFT = 7, 118 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 119 CORE_CLK_PLL_SEL_APLL = 0, 120 CORE_CLK_PLL_SEL_GPLL_DIV2, 121 CORE_DIV_CON_SHIFT = 0, 122 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 123 124 /* CRU_CLK_SEL1_CON */ 125 BUS_PCLK_DIV_SHIFT = 12, 126 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 127 BUS_HCLK_DIV_SHIFT = 8, 128 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 129 CORE_ACLK_DIV_SHIFT = 4, 130 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 131 CORE_PERI_DIV_SHIFT = 0, 132 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 133 134 /* CRU_CLKSEL10_CON */ 135 PERI_PLL_SEL_SHIFT = 14, 136 PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, 137 PERI_PLL_APLL = 0, 138 PERI_PLL_DPLL, 139 PERI_PLL_GPLL, 140 PERI_PCLK_DIV_SHIFT = 12, 141 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 142 PERI_HCLK_DIV_SHIFT = 8, 143 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 144 PERI_ACLK_DIV_SHIFT = 0, 145 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 146 147 /* CRU_CLKSEL11_CON */ 148 MMC0_PLL_SHIFT = 6, 149 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 150 MMC0_SEL_APLL = 0, 151 MMC0_SEL_GPLL, 152 MMC0_SEL_GPLL_DIV2, 153 MMC0_SEL_24M, 154 MMC0_DIV_SHIFT = 0, 155 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 156 157 /* CRU_CLKSEL12_CON */ 158 EMMC_PLL_SHIFT = 14, 159 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 160 EMMC_SEL_APLL = 0, 161 EMMC_SEL_GPLL, 162 EMMC_SEL_GPLL_DIV2, 163 EMMC_SEL_24M, 164 EMMC_DIV_SHIFT = 8, 165 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 166 167 /* CRU_SOFTRST5_CON */ 168 DDRCTRL_PSRST_SHIFT = 11, 169 DDRCTRL_SRST_SHIFT = 10, 170 DDRPHY_PSRST_SHIFT = 9, 171 DDRPHY_SRST_SHIFT = 8, 172 }; 173 #endif 174