arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon G

arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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armv8/fsl-lsch2: fix sdhc clock frequency value

The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock freq

armv8/fsl-lsch2: fix sdhc clock frequency value

The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Updating entries in Serdes Table

The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to

armv8: fsl-layerscape: Updating entries in Serdes Table

The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: ls2080a: remove obsolete stream ID partitioning support

Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PC

armv8: ls2080a: remove obsolete stream ID partitioning support

Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: lsch3: Enable WUO config for RNI-20 node

Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kush

armv8: lsch3: Enable WUO config for RNI-20 node

Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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arm64: Fix layerscape mmu setup

With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, w

arm64: Fix layerscape mmu setup

With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.

Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'next'

spl: arm: Make sure to include all of the u_boot_list entries

Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that

spl: arm: Make sure to include all of the u_boot_list entries

Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.

Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

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arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX

On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size.

arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX

On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size. Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

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arm64: Allow exceptions to return

Our current arm64 exception handlers all panic and never return to the
exception triggering code.

But if any handler wanted to continue execution after fixups, it

arm64: Allow exceptions to return

Our current arm64 exception handlers all panic and never return to the
exception triggering code.

But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.

This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).

Signed-off-by: Alexander Graf <agraf@suse.de>

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efi_loader: Add runtime services

After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since t

efi_loader: Add runtime services

After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.

This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.

We could maybe in the future map U-boot environment variables to EFI variables
here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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arm64: Only allow dcache disabled in SPL builds

Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
c

arm64: Only allow dcache disabled in SPL builds

Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.

Signed-off-by: Alexander Graf <agraf@suse.de>

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arm64: Remove non-full-va map code

By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove

arm64: Remove non-full-va map code

By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>

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zymqmp: Replace home grown mmu code with generic table approach

Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander

zymqmp: Replace home grown mmu code with generic table approach

Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>

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thunderx: Move mmu table into board file

The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will,

thunderx: Move mmu table into board file

The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.

Signed-off-by: Alexander Graf <agraf@suse.de>

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arm64: Make full va map code more dynamic

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k

arm64: Make full va map code more dynamic

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf <agraf@suse.de>

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arm64: Disable TTBR1 maps in EL1

When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

arm64: Disable TTBR1 maps in EL1

When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

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thunderx: Calculate TCR dynamically

Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to redu

thunderx: Calculate TCR dynamically

Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.

Signed-off-by: Alexander Graf <agraf@suse.de>

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omap4: Check warm reset for reboot mode validity

Since the SAR registers are filled with garbage on cold reset, this checks for a
warm reset to assert the validity of reboot mode.

Signed-off-by: Pa

omap4: Check warm reset for reboot mode validity

Since the SAR registers are filled with garbage on cold reset, this checks for a
warm reset to assert the validity of reboot mode.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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omap4: Reboot mode support

Reboot mode is written to SAR memory before reboot in the form of a string.

This mechanism is supported on OMAP4 by various TI kernels.

It is up to each board to make us

omap4: Reboot mode support

Reboot mode is written to SAR memory before reboot in the form of a string.

This mechanism is supported on OMAP4 by various TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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omap4: Properly enable USB PHY clocks

This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Koci

omap4: Properly enable USB PHY clocks

This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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omap-common: clocks-common: Setup USB DPLL when MUSB is in use

On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
to work properly. The internal PHY is used by default wi

omap-common: clocks-common: Setup USB DPLL when MUSB is in use

On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
to work properly. The internal PHY is used by default with the MUSB USB OTG
controller.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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Amazon Kindle Fire (first generation) codename kc1 support

The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.

It is using an OMAP4430 SoC G

Amazon Kindle Fire (first generation) codename kc1 support

The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.

It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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omap4: Move i2c clocks enable to enable_basic_clocks

I2C is often enabled withing the U-Boot SPL, thus those clocks are required to
be enabled early (especially when the bootrom doesn't enable them

omap4: Move i2c clocks enable to enable_basic_clocks

I2C is often enabled withing the U-Boot SPL, thus those clocks are required to
be enabled early (especially when the bootrom doesn't enable them for us).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespace

This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin
enable_basic_uboot_clocks. Also, a doubled whitespace is re

omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespace

This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin
enable_basic_uboot_clocks. Also, a doubled whitespace is removed.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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