| 8f2e2f15 | 18-Jul-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
mx6: clock: Fix the logic for reading axi_alt_sel
According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select 0 pl
mx6: clock: Fix the logic for reading axi_alt_sel
According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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| 66669fcf | 19-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c |
| 45684ae3 | 28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/PSCI: Fixup the device tree for PSCI
Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
ARMv8/PSCI: Fixup the device tree for PSCI
Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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| 032d5bb4 | 28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/Layerscape: switch SMP method accordingly
If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device nod
ARMv8/Layerscape: switch SMP method accordingly
If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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| f1dd4cad | 28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8/layerscape: Add FSL PPA support
The FSL Primary Protected Application (PPA) is a software component loaded during boot which runs in TrustZone and remains resident after boot.
Use the secure
ARMv8/layerscape: Add FSL PPA support
The FSL Primary Protected Application (PPA) is a software component loaded during boot which runs in TrustZone and remains resident after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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| b45db3b5 | 28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
ARMv8: add the secure monitor firmware framework
This framework is introduced for ARMv8 secure monitor mode firmware. The main functions of the framework are, on EL3, verify the firmware, load it to
ARMv8: add the secure monitor firmware framework
This framework is introduced for ARMv8 secure monitor mode firmware. The main functions of the framework are, on EL3, verify the firmware, load it to the secure memory and jump into it, and while it returned to U-Boot, do some necessary setups at the 'target exception level' that is determined by the respective secure firmware.
So far, the framework support only FIT format image, and need to define the name of which config node should be used in 'configurations' and the name of property for the raw secure firmware image in that config. The FIT image should be stored in Byte accessing memory, such as NOR Flash, or else it should be copied to main memory to use this framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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| 85cdf38e | 28-Jun-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches
This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the ass
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches
This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL.
Define the function mmu_setup() for fsl-layerscape to cover the weak one.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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| 5ad5823d | 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Convert to use common MMU framework
Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-
armv8: layerscape: Convert to use common MMU framework
Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios.
Signed-off-by: York Sun <york.sun@nxp.com>
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| be1a17ff | 13-Jul-2016 |
Stefan Agner <stefan.agner@toradex.com> |
mx7_common: use Kconfig for ARMv7 non-secure mode
Use existing Kconfig symbols to let the user configure whether to build a U-Boot with non-secure mode support or not. This also allows to enable vir
mx7_common: use Kconfig for ARMv7 non-secure mode
Use existing Kconfig symbols to let the user configure whether to build a U-Boot with non-secure mode support or not. This also allows to enable virtualization extension easily.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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| ec7fde3e | 13-Jul-2016 |
Stefan Agner <stefan.agner@toradex.com> |
mx7: set soc environment according to exact SoC type
This can be useful if the same U-Boot binary is used for boards available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.
mx7: set soc environment according to exact SoC type
This can be useful if the same U-Boot binary is used for boards available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| 62a3b7dd | 15-Jul-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Various, unrelated tree-wide typo fixes.
Fix a number of typos, including:
* "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" ->
Various, unrelated tree-wide typo fixes.
Fix a number of typos, including:
* "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable"
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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| cd4b0c5f | 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add support of non-identical mapping
Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping.
armv8: mmu: Add support of non-identical mapping
Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
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| f733d466 | 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: mmu: split block if necessary
When page tables are created, allow later table to be created on previous block entry. Splitting block feature is already working with current code. This patch o
armv8: mmu: split block if necessary
When page tables are created, allow later table to be created on previous block entry. Splitting block feature is already working with current code. This patch only rearranges the code order and adds one condition to call split_block().
Signed-off-by: York Sun <york.sun@nxp.com>
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| 252cdb46 | 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: mmu: house cleaning
Make setup_pgtages() and get_tcr() available for platform code to customize MMU tables. Remove unintentional call of create_table().
Signed-off-by: York Sun <york.sun@nxp
armv8: mmu: house cleaning
Make setup_pgtages() and get_tcr() available for platform code to customize MMU tables. Remove unintentional call of create_table().
Signed-off-by: York Sun <york.sun@nxp.com>
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| e61a7534 | 24-Jun-2016 |
York Sun <york.sun@nxp.com> |
armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure.
Signed-off-
armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
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| 1f9ef0dc | 15-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi |
| b7073965 | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S
Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address.
Make p
ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S
Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address.
Make psci_get_cpu_stack_top a local function, as it should only be used in armv7/psci.S and only by psci_stack_setup.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 6e6622de | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: PSCI: Switch to per-CPU target PC storage in secure data section
Now that we have a secure data section and space to store per-CPU target PC address, switch to it instead of storing the target
ARM: PSCI: Switch to per-CPU target PC storage in secure data section
Now that we have a secure data section and space to store per-CPU target PC address, switch to it instead of storing the target PC on the stack.
Also save clobbered r4-r7 registers on the stack and restore them on return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 45c334e6 | 05-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: PSCI: Add helper functions to access per-CPU target PC storage
Now that we have a data section, add helper functions to save and fetch per-CPU target PC.
Signed-off-by: Chen-Yu Tsai <wens@csie
ARM: PSCI: Add helper functions to access per-CPU target PC storage
Now that we have a data section, add helper functions to save and fetch per-CPU target PC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| a5aa7ff3 | 05-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: Add secure section for initialized data
The secure monitor may need to store global or static values within the secure section of memory, such as target PC or CPU power status.
Signed-off-by:
ARM: Add secure section for initialized data
The secure monitor may need to store global or static values within the secure section of memory, such as target PC or CPU power status.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| afc1f65f | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: Move __secure definition to common asm/secure.h
sunxi and i.mx7 both define the __secure modifier to put functions in the secure section. Move this to a common place.
Signed-off-by: Chen-Yu Ts
ARM: Move __secure definition to common asm/secure.h
sunxi and i.mx7 both define the __secure modifier to put functions in the secure section. Move this to a common place.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 3eff6818 | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure section
As the PSCI implementation grows, we might exceed the size of the secure memory that holds the firmware.
Add a configurable CO
ARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure section
As the PSCI implementation grows, we might exceed the size of the secure memory that holds the firmware.
Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define how much secure memory is available. The linker then checks the size of the whole secure section against this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 28f90357 | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: PSCI: Remove unused psci_text_end symbol
psci_text_end was used to calculate the PSCI stack address following the secure monitor text. Now that we have an explicit secure stack section, this is
ARM: PSCI: Remove unused psci_text_end symbol
psci_text_end was used to calculate the PSCI stack address following the secure monitor text. Now that we have an explicit secure stack section, this is no longer used.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 8c0ef7fa | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: PSCI: Allocate PSCI stack in secure stack section
Now that we have a secure stack section that guarantees usable memory, allocate the PSCI stacks in that section.
Also add a diagram detailing
ARM: PSCI: Allocate PSCI stack in secure stack section
Now that we have a secure stack section that guarantees usable memory, allocate the PSCI stacks in that section.
Also add a diagram detailing how the stacks are placed in memory.
Reserved space for the target PC remains unchanged. This should be moved to global variables within a secure data section in the future.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 980d6a55 | 19-Jun-2016 |
Chen-Yu Tsai <wens@csie.org> |
ARM: Add an empty secure stack section
Until now we've been using memory beyond psci_text_end as stack space for the secure monitor or PSCI implementation, even if space was not allocated for it.
T
ARM: Add an empty secure stack section
Until now we've been using memory beyond psci_text_end as stack space for the secure monitor or PSCI implementation, even if space was not allocated for it.
This was partially fixed in ("ARM: allocate extra space for PSCI stack in secure section during link phase"). However, calculating stack space from psci_text_end in one place, while allocating the space in another is error prone.
This patch adds a separate empty secure stack section, with space for CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also __secure_stack_start and __secure_stack_end symbols. The linker script handles calculating the correct VMAs for the stack section. For platforms that relocate/copy the secure monitor before using it, the space is not allocated in the executable, saving space.
For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page of stack space for 4 CPUs is allocated, matching the previous behavior.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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