1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/errno.h> 10 #include <asm/system.h> 11 #include <asm/armv8/mmu.h> 12 #include <asm/io.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/soc.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/speed.h> 17 #ifdef CONFIG_MP 18 #include <asm/arch/mp.h> 19 #endif 20 #include <fm_eth.h> 21 #include <fsl_debug_server.h> 22 #include <fsl-mc/fsl_mc.h> 23 #ifdef CONFIG_FSL_ESDHC 24 #include <fsl_esdhc.h> 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 struct mm_region *mem_map = early_map; 30 31 void cpu_name(char *name) 32 { 33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 34 unsigned int i, svr, ver; 35 36 svr = gur_in32(&gur->svr); 37 ver = SVR_SOC_VER(svr); 38 39 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 40 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { 41 strcpy(name, cpu_type_list[i].name); 42 43 if (IS_E_PROCESSOR(svr)) 44 strcat(name, "E"); 45 break; 46 } 47 48 if (i == ARRAY_SIZE(cpu_type_list)) 49 strcpy(name, "unknown"); 50 } 51 52 #ifndef CONFIG_SYS_DCACHE_OFF 53 /* 54 * To start MMU before DDR is available, we create MMU table in SRAM. 55 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three 56 * levels of translation tables here to cover 40-bit address space. 57 * We use 4KB granule size, with 40 bits physical address, T0SZ=24 58 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. 59 * Note, the debug print in cache_v8.c is not usable for debugging 60 * these early MMU tables because UART is not yet available. 61 */ 62 static inline void early_mmu_setup(void) 63 { 64 unsigned int el = current_el(); 65 66 /* global data is already setup, no allocation yet */ 67 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; 68 gd->arch.tlb_fillptr = gd->arch.tlb_addr; 69 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; 70 71 /* Create early page tables */ 72 setup_pgtables(); 73 74 /* point TTBR to the new table */ 75 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 76 get_tcr(el, NULL, NULL) & 77 ~(TCR_ORGN_MASK | TCR_IRGN_MASK), 78 MEMORY_ATTRIBUTES); 79 80 set_sctlr(get_sctlr() | CR_M); 81 } 82 83 /* 84 * The final tables look similar to early tables, but different in detail. 85 * These tables are in DRAM. Sub tables are added to enable cache for 86 * QBMan and OCRAM. 87 * 88 * Put the MMU table in secure memory if gd->arch.secure_ram is valid. 89 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. 90 */ 91 static inline void final_mmu_setup(void) 92 { 93 u64 tlb_addr_save = gd->arch.tlb_addr; 94 unsigned int el = current_el(); 95 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 96 int index; 97 #endif 98 99 mem_map = final_map; 100 101 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 102 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 103 if (el == 3) { 104 /* 105 * Only use gd->arch.secure_ram if the address is 106 * recalculated. Align to 4KB for MMU table. 107 */ 108 /* put page tables in secure ram */ 109 index = ARRAY_SIZE(final_map) - 2; 110 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; 111 final_map[index].virt = gd->arch.secure_ram & ~0x3; 112 final_map[index].phys = final_map[index].virt; 113 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; 114 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; 115 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; 116 tlb_addr_save = gd->arch.tlb_addr; 117 } else { 118 /* Use allocated (board_f.c) memory for TLB */ 119 tlb_addr_save = gd->arch.tlb_allocated; 120 gd->arch.tlb_addr = tlb_addr_save; 121 } 122 } 123 #endif 124 125 /* Reset the fill ptr */ 126 gd->arch.tlb_fillptr = tlb_addr_save; 127 128 /* Create normal system page tables */ 129 setup_pgtables(); 130 131 /* Create emergency page tables */ 132 gd->arch.tlb_addr = gd->arch.tlb_fillptr; 133 gd->arch.tlb_emerg = gd->arch.tlb_addr; 134 setup_pgtables(); 135 gd->arch.tlb_addr = tlb_addr_save; 136 137 /* flush new MMU table */ 138 flush_dcache_range(gd->arch.tlb_addr, 139 gd->arch.tlb_addr + gd->arch.tlb_size); 140 141 /* point TTBR to the new table */ 142 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), 143 MEMORY_ATTRIBUTES); 144 /* 145 * MMU is already enabled, just need to invalidate TLB to load the 146 * new table. The new table is compatible with the current table, if 147 * MMU somehow walks through the new table before invalidation TLB, 148 * it still works. So we don't need to turn off MMU here. 149 */ 150 } 151 152 u64 get_page_table_size(void) 153 { 154 return 0x10000; 155 } 156 157 int arch_cpu_init(void) 158 { 159 icache_enable(); 160 __asm_invalidate_dcache_all(); 161 __asm_invalidate_tlb_all(); 162 early_mmu_setup(); 163 set_sctlr(get_sctlr() | CR_C); 164 return 0; 165 } 166 167 void mmu_setup(void) 168 { 169 final_mmu_setup(); 170 } 171 172 /* 173 * This function is called from common/board_r.c. 174 * It recreates MMU table in main memory. 175 */ 176 void enable_caches(void) 177 { 178 mmu_setup(); 179 __asm_invalidate_tlb_all(); 180 icache_enable(); 181 dcache_enable(); 182 } 183 #endif 184 185 static inline u32 initiator_type(u32 cluster, int init_id) 186 { 187 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 188 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 189 u32 type = 0; 190 191 type = gur_in32(&gur->tp_ityp[idx]); 192 if (type & TP_ITYP_AV) 193 return type; 194 195 return 0; 196 } 197 198 u32 cpu_mask(void) 199 { 200 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 201 int i = 0, count = 0; 202 u32 cluster, type, mask = 0; 203 204 do { 205 int j; 206 207 cluster = gur_in32(&gur->tp_cluster[i].lower); 208 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 209 type = initiator_type(cluster, j); 210 if (type) { 211 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 212 mask |= 1 << count; 213 count++; 214 } 215 } 216 i++; 217 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 218 219 return mask; 220 } 221 222 /* 223 * Return the number of cores on this SOC. 224 */ 225 int cpu_numcores(void) 226 { 227 return hweight32(cpu_mask()); 228 } 229 230 int fsl_qoriq_core_to_cluster(unsigned int core) 231 { 232 struct ccsr_gur __iomem *gur = 233 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 234 int i = 0, count = 0; 235 u32 cluster; 236 237 do { 238 int j; 239 240 cluster = gur_in32(&gur->tp_cluster[i].lower); 241 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 242 if (initiator_type(cluster, j)) { 243 if (count == core) 244 return i; 245 count++; 246 } 247 } 248 i++; 249 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 250 251 return -1; /* cannot identify the cluster */ 252 } 253 254 u32 fsl_qoriq_core_to_type(unsigned int core) 255 { 256 struct ccsr_gur __iomem *gur = 257 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 258 int i = 0, count = 0; 259 u32 cluster, type; 260 261 do { 262 int j; 263 264 cluster = gur_in32(&gur->tp_cluster[i].lower); 265 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 266 type = initiator_type(cluster, j); 267 if (type) { 268 if (count == core) 269 return type; 270 count++; 271 } 272 } 273 i++; 274 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 275 276 return -1; /* cannot identify the cluster */ 277 } 278 279 uint get_svr(void) 280 { 281 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 282 283 return gur_in32(&gur->svr); 284 } 285 286 #ifdef CONFIG_DISPLAY_CPUINFO 287 int print_cpuinfo(void) 288 { 289 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 290 struct sys_info sysinfo; 291 char buf[32]; 292 unsigned int i, core; 293 u32 type, rcw, svr = gur_in32(&gur->svr); 294 295 puts("SoC: "); 296 297 cpu_name(buf); 298 printf(" %s (0x%x)\n", buf, svr); 299 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 300 get_sys_info(&sysinfo); 301 puts("Clock Configuration:"); 302 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { 303 if (!(i % 3)) 304 puts("\n "); 305 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); 306 printf("CPU%d(%s):%-4s MHz ", core, 307 type == TY_ITYP_VER_A7 ? "A7 " : 308 (type == TY_ITYP_VER_A53 ? "A53" : 309 (type == TY_ITYP_VER_A57 ? "A57" : " ")), 310 strmhz(buf, sysinfo.freq_processor[core])); 311 } 312 printf("\n Bus: %-4s MHz ", 313 strmhz(buf, sysinfo.freq_systembus)); 314 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); 315 #ifdef CONFIG_SYS_DPAA_FMAN 316 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); 317 #endif 318 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 319 if (soc_has_dp_ddr()) { 320 printf(" DP-DDR: %-4s MT/s", 321 strmhz(buf, sysinfo.freq_ddrbus2)); 322 } 323 #endif 324 puts("\n"); 325 326 /* 327 * Display the RCW, so that no one gets confused as to what RCW 328 * we're actually using for this boot. 329 */ 330 puts("Reset Configuration Word (RCW):"); 331 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 332 rcw = gur_in32(&gur->rcwsr[i]); 333 if ((i % 4) == 0) 334 printf("\n %08x:", i * 4); 335 printf(" %08x", rcw); 336 } 337 puts("\n"); 338 339 return 0; 340 } 341 #endif 342 343 #ifdef CONFIG_FSL_ESDHC 344 int cpu_mmc_init(bd_t *bis) 345 { 346 return fsl_esdhc_mmc_init(bis); 347 } 348 #endif 349 350 int cpu_eth_init(bd_t *bis) 351 { 352 int error = 0; 353 354 #ifdef CONFIG_FSL_MC_ENET 355 error = fsl_mc_ldpaa_init(bis); 356 #endif 357 #ifdef CONFIG_FMAN_ENET 358 fm_standard_init(bis); 359 #endif 360 return error; 361 } 362 363 int arch_early_init_r(void) 364 { 365 #ifdef CONFIG_MP 366 int rv = 1; 367 #endif 368 369 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 370 erratum_a009635(); 371 #endif 372 373 #ifdef CONFIG_MP 374 rv = fsl_layerscape_wake_seconday_cores(); 375 if (rv) 376 printf("Did not wake secondary cores\n"); 377 #endif 378 379 #ifdef CONFIG_SYS_HAS_SERDES 380 fsl_serdes_init(); 381 #endif 382 #ifdef CONFIG_FMAN_ENET 383 fman_enet_init(); 384 #endif 385 return 0; 386 } 387 388 int timer_init(void) 389 { 390 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; 391 #ifdef CONFIG_FSL_LSCH3 392 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; 393 #endif 394 #ifdef CONFIG_LS2080A 395 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; 396 #endif 397 #ifdef COUNTER_FREQUENCY_REAL 398 unsigned long cntfrq = COUNTER_FREQUENCY_REAL; 399 400 /* Update with accurate clock frequency */ 401 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); 402 #endif 403 404 #ifdef CONFIG_FSL_LSCH3 405 /* Enable timebase for all clusters. 406 * It is safe to do so even some clusters are not enabled. 407 */ 408 out_le32(cltbenr, 0xf); 409 #endif 410 411 #ifdef CONFIG_LS2080A 412 /* 413 * In certain Layerscape SoCs, the clock for each core's 414 * has an enable bit in the PMU Physical Core Time Base Enable 415 * Register (PCTBENR), which allows the watchdog to operate. 416 */ 417 setbits_le32(pctbenr, 0xff); 418 #endif 419 420 /* Enable clock for timer 421 * This is a global setting. 422 */ 423 out_le32(cntcr, 0x1); 424 425 return 0; 426 } 427 428 void reset_cpu(ulong addr) 429 { 430 u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; 431 u32 val; 432 433 /* Raise RESET_REQ_B */ 434 val = scfg_in32(rstcr); 435 val |= 0x02; 436 scfg_out32(rstcr, val); 437 } 438 439 phys_size_t board_reserve_ram_top(phys_size_t ram_size) 440 { 441 phys_size_t ram_top = ram_size; 442 443 #ifdef CONFIG_SYS_MEM_TOP_HIDE 444 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function 445 #endif 446 /* Carve the Debug Server private DRAM block from the end of DRAM */ 447 #ifdef CONFIG_FSL_DEBUG_SERVER 448 ram_top -= debug_server_get_dram_block_size(); 449 #endif 450 451 /* Carve the MC private DRAM block from the end of DRAM */ 452 #ifdef CONFIG_FSL_MC_ENET 453 ram_top -= mc_get_dram_block_size(); 454 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); 455 #endif 456 457 return ram_top; 458 } 459