| 2ab28103 | 14-May-2012 |
Tom Rini <trini@ti.com> |
am33xx: Do not call init_timer twice
We do not need to call init_timer both in SPL and U-Boot itself, just
SPL needs to initialize the timer.
Signed-off-by: Tom Rini <trini@ti.com> |
| 76e350b7 | 30-May-2012 |
Tom Warren <twarren@nvidia.com> |
arm: Tegra: Use ODMDATA from BCT in IRAM
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Boo
arm: Tegra: Use ODMDATA from BCT in IRAM
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
show more ...
|
| f3717ac5 | 14-May-2012 |
amartin@nvidia.com <amartin@nvidia.com> |
tegra: override compiler flags for low level init code
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=a
tegra: override compiler flags for low level init code
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9. While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 27c4a331 | 19-Apr-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes
tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| d1e46079 | 16-May-2012 |
Stephen Warren <swarren@nvidia.com> |
tegra: add SDMMC1 on SDIO1 funcmux entry
This will be used on TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com> |
| a2cfe63e | 16-May-2012 |
Lucas Stach <dev@lynxeye.de> |
tegra: add SDIO1 funcmux entry for UARTA
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <
tegra: add SDIO1 funcmux entry for UARTA
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| e21649be | 16-May-2012 |
Stephen Warren <swarren@nvidia.com> |
tegra: add UART1 on GPU funcmux entry
TrimSlice uses UART1 on the GPU pingroup.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com> |
| b9607e70 | 14-May-2012 |
Stephen Warren <swarren@nvidia.com> |
tegra: add alternate UART1 funcmux entry
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <t
tegra: add alternate UART1 funcmux entry
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 287e3ad4 | 20-May-2012 |
Anatolij Gustschin <agust@denx.de> |
arch/arm/cpu/ixp/npe/npe.c: Fix build warning
Fix:
npe.c: In function 'npe_initialize':
npe.c:630:13: warning: assignment from incompatible pointer type
Signed-off-by: Anatolij Gustschin <agust@den
arch/arm/cpu/ixp/npe/npe.c: Fix build warning
Fix:
npe.c: In function 'npe_initialize':
npe.c:630:13: warning: assignment from incompatible pointer type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
show more ...
|
| a3c3fabb | 07-May-2012 |
Matt Porter <mporter@ti.com> |
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.
This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.
Signed-off-by: Matt Porter <mporter@ti.com>
show more ...
|
| 2d622b03 | 25-Apr-2012 |
Tero Kristo <t-kristo@ti.com> |
omap4: do not enable auxiliary cores
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on wi
omap4: do not enable auxiliary cores
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: R Sricharan <r.sricharan@ti.com>
show more ...
|
| 71ee921d | 25-Apr-2012 |
Tero Kristo <t-kristo@ti.com> |
omap4: do not enable fs-usb module
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Signed-off-by: Tero K
omap4: do not enable fs-usb module
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
show more ...
|
| b8cb5194 | 01-May-2012 |
Lucas Stach <dev@lynxeye.de> |
tegra2: trivially enable 13 mhz crystal frequency
This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nv
tegra2: trivially enable 13 mhz crystal frequency
This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 7e91f40d | 17-Apr-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add keyboard support to funcmux
Add funcmux support for the default keyboard mapping.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com> |
| c5179da9 | 02-Apr-2012 |
Yen Lin <yelin@nvidia.com> |
tegra: Setup PMC scratch info from ap20 setup
Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signe
tegra: Setup PMC scratch info from ap20 setup
Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 6570438a | 10-Apr-2012 |
Yen Lin <yelin@nvidia.com> |
tegra: Add warmboot implementation
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg
tegra: Add warmboot implementation
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 6860b4a1 | 02-Apr-2012 |
Jimmy Zhang <jimmzhang@nvidia.com> |
tegra: Add PMU to manage power supplies
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
tegra: Add PMU to manage power supplies
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 0e35ad05 | 02-Apr-2012 |
Jimmy Zhang <jimmzhang@nvidia.com> |
tegra: Add EMC support for optimal memory timings
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass
tegra: Add EMC support for optimal memory timings
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| d515362d | 02-Apr-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add thi
tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 2a6f036a | 02-Apr-2012 |
Yen Lin <yelin@nvidia.com> |
tegra: Add crypto library for warmboot code
Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-
tegra: Add crypto library for warmboot code
Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| ffc76482 | 02-Apr-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add functions to access low-level Osc/PLL details
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warm
tegra: Add functions to access low-level Osc/PLL details
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| f9f3e1b8 | 02-Apr-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Move ap20.h header into arch location
We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off
tegra: Move ap20.h header into arch location
We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| a35925b8 | 10-May-2012 |
Simon Glass <sjg@chromium.org> |
Add abs() macro to return absolute value
This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add abs() macro to return absolute value
This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
show more ...
|
| 39007ec8 | 01-May-2012 |
Marek Vasut <marex@denx.de> |
i.MX28: Avoid redefining serial_put[cs]()
Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@
i.MX28: Avoid redefining serial_put[cs]()
Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
show more ...
|
| 7dec1bd1 | 01-May-2012 |
Marek Vasut <marek.vasut@gmail.com> |
i.MX28: Add battery boot components to SPL
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabi
i.MX28: Add battery boot components to SPL
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
show more ...
|