EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Sign

EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0

save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch

arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0

save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch removes save_boot_params_default() and put the equivalent in start.S

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>

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tegra20: Remove armv4t build flags

These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate

tegra20: Remove armv4t build flags

These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: enable SPL for tegra20 boards

Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.

Signed-

tegra20: enable SPL for tegra20 boards

Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: move SDRAM param save to later in boot

Move warmboot_save_sdram_params() to later in the boot sequence. This
code relies on devicetree to get the address of the memory controller
and with

tegra20: move SDRAM param save to later in boot

Move warmboot_save_sdram_params() to later in the boot sequence. This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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ARM: add tegra20 support to arm720t

Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI

ARM: add tegra20 support to arm720t

Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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ARM: Fix arm720t SPL build

Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocatio

ARM: Fix arm720t SPL build

Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common

In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will

tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common

In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: rename tegra2 -> tegra20

This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidi

tegra20: rename tegra2 -> tegra20

This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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ARM: add basic support for the Broadcom BCM2835 SoC

This SoC is used in the Raspberry Pi, for example.

For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-

ARM: add basic support for the Broadcom BCM2835 SoC

This SoC is used in the Raspberry Pi, for example.

For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.

Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.

GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

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ARM: arm1176: enable instruction cache in arch_cpu_init()

Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107

ARM: arm1176: enable instruction cache in arch_cpu_init()

Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.

Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

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snowball: Adding board specific cache cleanup routine

Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.

Signed-off-by: Mathieu Poirier <mathieu.poirier@

snowball: Adding board specific cache cleanup routine

Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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armv7: Adding cpu specific cache managmenent

Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-of

armv7: Adding cpu specific cache managmenent

Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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u8500: Enabling power to MMC device on AB8500 V2

Register mapping has changed on power control chip between
the first and second revision.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org

u8500: Enabling power to MMC device on AB8500 V2

Register mapping has changed on power control chip between
the first and second revision.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>

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u8500: Moving processor-specific functions to cpu area.

Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multipl

u8500: Moving processor-specific functions to cpu area.

Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>

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snowball: Moving to ux500.v2 addess scheme for PRCMU access

Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.

Signed-off-by: Mathi

snowball: Moving to ux500.v2 addess scheme for PRCMU access

Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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snowball: Adding CPU clock initialisation

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

snowball: Adding architecture dependent initialisation

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John R

snowball: Adding architecture dependent initialisation

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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u8500: Moving prcmu to cpu directory

This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: J

u8500: Moving prcmu to cpu directory

This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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davinci, c6x: Always use C version of reset code

We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller o

davinci, c6x: Always use C version of reset code

We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller on Davinci.

Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

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am33xx evm: Update secure_emif_sdram_config during ddr init

This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume

am33xx evm: Update secure_emif_sdram_config during ddr init

This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>

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da8xx/hawkboard: Add support for ohci host controller

Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

da8xx/hawkboard: Add support for ohci host controller

Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>

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armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack

Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.

Tested

armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack

Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.

Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>

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omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms

Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all arm

omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms

Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.

Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Add support, update omap3 McSPI driver

Signed-off-by: Tom Rini <trini@ti.com>