1/* 2 * armboot - Startup Code for ARM720 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#include <asm-offsets.h> 27#include <config.h> 28#include <version.h> 29#include <asm/hardware.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b reset 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46#ifdef CONFIG_LPC2292 47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ 48#else 49 ldr pc, _not_used 50#endif 51 ldr pc, _irq 52 ldr pc, _fiq 53 54#ifdef CONFIG_SPL_BUILD 55_undefined_instruction: .word _undefined_instruction 56_software_interrupt: .word _software_interrupt 57_prefetch_abort: .word _prefetch_abort 58_data_abort: .word _data_abort 59_not_used: .word _not_used 60_irq: .word _irq 61_fiq: .word _fiq 62#else 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70#endif /* CONFIG_SPL_BUILD */ 71 72 .balignl 16,0xdeadbeef 73 74 75/* 76 ************************************************************************* 77 * 78 * Startup Code (reset vector) 79 * 80 * do important init only if we don't start from RAM! 81 * relocate armboot to ram 82 * setup stack 83 * jump to second stage 84 * 85 ************************************************************************* 86 */ 87 88.globl _TEXT_BASE 89_TEXT_BASE: 90 .word CONFIG_SYS_TEXT_BASE 91 92/* 93 * These are defined in the board-specific linker script. 94 * Subtracting _start from them lets the linker put their 95 * relative position in the executable instead of leaving 96 * them null. 97 */ 98.globl _bss_start_ofs 99_bss_start_ofs: 100 .word __bss_start - _start 101 102.globl _bss_end_ofs 103_bss_end_ofs: 104 .word __bss_end__ - _start 105 106.globl _end_ofs 107_end_ofs: 108 .word _end - _start 109 110#ifdef CONFIG_USE_IRQ 111/* IRQ stack memory (calculated at run-time) */ 112.globl IRQ_STACK_START 113IRQ_STACK_START: 114 .word 0x0badc0de 115 116/* IRQ stack memory (calculated at run-time) */ 117.globl FIQ_STACK_START 118FIQ_STACK_START: 119 .word 0x0badc0de 120#endif 121 122/* IRQ stack memory (calculated at run-time) + 8 bytes */ 123.globl IRQ_STACK_START_IN 124IRQ_STACK_START_IN: 125 .word 0x0badc0de 126 127/* 128 * the actual reset code 129 */ 130 131reset: 132 /* 133 * set the cpu to SVC32 mode 134 */ 135 mrs r0,cpsr 136 bic r0,r0,#0x1f 137 orr r0,r0,#0xd3 138 msr cpsr,r0 139 140 /* 141 * we do sys-critical inits only at reboot, 142 * not when booting from ram! 143 */ 144#ifndef CONFIG_SKIP_LOWLEVEL_INIT 145 bl cpu_init_crit 146#endif 147 148#ifdef CONFIG_LPC2292 149 bl lowlevel_init 150#endif 151 152/* Set stackpointer in internal RAM to call board_init_f */ 153call_board_init_f: 154 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 155 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 156 ldr r0,=0x00000000 157 bl board_init_f 158 159/*------------------------------------------------------------------------------*/ 160 161/* 162 * void relocate_code (addr_sp, gd, addr_moni) 163 * 164 * This "function" does not return, instead it continues in RAM 165 * after relocating the monitor code. 166 * 167 */ 168 .globl relocate_code 169relocate_code: 170 mov r4, r0 /* save addr_sp */ 171 mov r5, r1 /* save addr of gd */ 172 mov r6, r2 /* save addr of destination */ 173 174 /* Set up the stack */ 175stack_setup: 176 mov sp, r4 177 178 adr r0, _start 179 cmp r0, r6 180 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 181 beq clear_bss /* skip relocation */ 182 mov r1, r6 /* r1 <- scratch for copy_loop */ 183 ldr r3, _bss_start_ofs 184 add r2, r0, r3 /* r2 <- source end address */ 185 186copy_loop: 187 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 188 stmia r1!, {r9-r10} /* copy to target address [r1] */ 189 cmp r0, r2 /* until source end address [r2] */ 190 blo copy_loop 191 192#ifndef CONFIG_SPL_BUILD 193 /* 194 * fix .rel.dyn relocations 195 */ 196 ldr r0, _TEXT_BASE /* r0 <- Text base */ 197 sub r9, r6, r0 /* r9 <- relocation offset */ 198 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 199 add r10, r10, r0 /* r10 <- sym table in FLASH */ 200 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 201 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 202 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 203 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 204fixloop: 205 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 206 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 207 ldr r1, [r2, #4] 208 and r7, r1, #0xff 209 cmp r7, #23 /* relative fixup? */ 210 beq fixrel 211 cmp r7, #2 /* absolute fixup? */ 212 beq fixabs 213 /* ignore unknown type of fixup */ 214 b fixnext 215fixabs: 216 /* absolute fix: set location to (offset) symbol value */ 217 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 218 add r1, r10, r1 /* r1 <- address of symbol in table */ 219 ldr r1, [r1, #4] /* r1 <- symbol value */ 220 add r1, r1, r9 /* r1 <- relocated sym addr */ 221 b fixnext 222fixrel: 223 /* relative fix: increase location by offset */ 224 ldr r1, [r0] 225 add r1, r1, r9 226fixnext: 227 str r1, [r0] 228 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 229 cmp r2, r3 230 blo fixloop 231#endif 232 233clear_bss: 234#ifndef CONFIG_SPL_BUILD 235 ldr r0, _bss_start_ofs 236 ldr r1, _bss_end_ofs 237 mov r4, r6 /* reloc addr */ 238 add r0, r0, r4 239 add r1, r1, r4 240 mov r2, #0x00000000 /* clear */ 241 242clbss_l:cmp r0, r1 /* clear loop... */ 243 bhs clbss_e /* if reached end of bss, exit */ 244 str r2, [r0] 245 add r0, r0, #4 246 b clbss_l 247clbss_e: 248 249 bl coloured_LED_init 250 bl red_led_on 251#endif 252 253/* 254 * We are done. Do not return, instead branch to second part of board 255 * initialization, now running from RAM. 256 */ 257 ldr r0, _board_init_r_ofs 258 adr r1, _start 259 add lr, r0, r1 260 add lr, lr, r9 261 /* setup parameters for board_init_r */ 262 mov r0, r5 /* gd_t */ 263 mov r1, r6 /* dest_addr */ 264 /* jump to it ... */ 265 mov pc, lr 266 267_board_init_r_ofs: 268 .word board_init_r - _start 269 270_rel_dyn_start_ofs: 271 .word __rel_dyn_start - _start 272_rel_dyn_end_ofs: 273 .word __rel_dyn_end - _start 274_dynsym_start_ofs: 275 .word __dynsym_start - _start 276 277/* 278 ************************************************************************* 279 * 280 * CPU_init_critical registers 281 * 282 * setup important registers 283 * setup memory timing 284 * 285 ************************************************************************* 286 */ 287 288#if defined(CONFIG_LPC2292) 289PLLCFG_ADR: .word PLLCFG 290PLLFEED_ADR: .word PLLFEED 291PLLCON_ADR: .word PLLCON 292PLLSTAT_ADR: .word PLLSTAT 293VPBDIV_ADR: .word VPBDIV 294MEMMAP_ADR: .word MEMMAP 295 296#endif 297 298cpu_init_crit: 299#if defined(CONFIG_NETARM) 300 /* 301 * prior to software reset : need to set pin PORTC4 to be *HRESET 302 */ 303 ldr r0, =NETARM_GEN_MODULE_BASE 304 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ 305 NETARM_GEN_PORT_DIR(0x10)) 306 str r1, [r0, #+NETARM_GEN_PORTC] 307 /* 308 * software reset : see HW Ref. Guide 8.2.4 : Software Service register 309 * for an explanation of this process 310 */ 311 ldr r0, =NETARM_GEN_MODULE_BASE 312 ldr r1, =NETARM_GEN_SW_SVC_RESETA 313 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 314 ldr r1, =NETARM_GEN_SW_SVC_RESETB 315 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 316 ldr r1, =NETARM_GEN_SW_SVC_RESETA 317 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 318 ldr r1, =NETARM_GEN_SW_SVC_RESETB 319 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 320 /* 321 * setup PLL and System Config 322 */ 323 ldr r0, =NETARM_GEN_MODULE_BASE 324 325 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ 326 NETARM_GEN_SYS_CFG_BUSFULL | \ 327 NETARM_GEN_SYS_CFG_USER_EN | \ 328 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ 329 NETARM_GEN_SYS_CFG_BUSARB_INT | \ 330 NETARM_GEN_SYS_CFG_BUSMON_EN ) 331 332 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] 333 334#ifndef CONFIG_NETARM_PLL_BYPASS 335 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ 336 NETARM_GEN_PLL_CTL_POLTST_DEF | \ 337 NETARM_GEN_PLL_CTL_INDIV(1) | \ 338 NETARM_GEN_PLL_CTL_ICP_DEF | \ 339 NETARM_GEN_PLL_CTL_OUTDIV(2) ) 340 str r1, [r0, #+NETARM_GEN_PLL_CONTROL] 341#endif 342 343 /* 344 * mask all IRQs by clearing all bits in the INTMRs 345 */ 346 mov r1, #0 347 ldr r0, =NETARM_GEN_MODULE_BASE 348 str r1, [r0, #+NETARM_GEN_INTR_ENABLE] 349 350#elif defined(CONFIG_S3C4510B) 351 352 /* 353 * Mask off all IRQ sources 354 */ 355 ldr r1, =REG_INTMASK 356 ldr r0, =0x3FFFFF 357 str r0, [r1] 358 359 /* 360 * Disable Cache 361 */ 362 ldr r0, =REG_SYSCFG 363 ldr r1, =0x83ffffa0 /* cache-disabled */ 364 str r1, [r0] 365 366#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 367 /* No specific initialisation for IntegratorAP/CM720T as yet */ 368#elif defined(CONFIG_LPC2292) 369 /* Set-up PLL */ 370 mov r3, #0xAA 371 mov r4, #0x55 372 /* First disconnect and disable the PLL */ 373 ldr r0, PLLCON_ADR 374 mov r1, #0x00 375 str r1, [r0] 376 ldr r0, PLLFEED_ADR /* start feed sequence */ 377 str r3, [r0] 378 str r4, [r0] /* feed sequence done */ 379 /* Set new M and P values */ 380 ldr r0, PLLCFG_ADR 381 mov r1, #0x23 /* M=4 and P=2 */ 382 str r1, [r0] 383 ldr r0, PLLFEED_ADR /* start feed sequence */ 384 str r3, [r0] 385 str r4, [r0] /* feed sequence done */ 386 /* Then enable the PLL */ 387 ldr r0, PLLCON_ADR 388 mov r1, #0x01 /* PLL enable bit */ 389 str r1, [r0] 390 ldr r0, PLLFEED_ADR /* start feed sequence */ 391 str r3, [r0] 392 str r4, [r0] /* feed sequence done */ 393 /* Wait for the lock */ 394 ldr r0, PLLSTAT_ADR 395 mov r1, #0x400 /* lock bit */ 396lock_loop: 397 ldr r2, [r0] 398 and r2, r1, r2 399 cmp r2, #0 400 beq lock_loop 401 /* And finally connect the PLL */ 402 ldr r0, PLLCON_ADR 403 mov r1, #0x03 /* PLL enable bit and connect bit */ 404 str r1, [r0] 405 ldr r0, PLLFEED_ADR /* start feed sequence */ 406 str r3, [r0] 407 str r4, [r0] /* feed sequence done */ 408 /* Set-up VPBDIV register */ 409 ldr r0, VPBDIV_ADR 410 mov r1, #0x01 /* VPB clock is same as process clock */ 411 str r1, [r0] 412#else 413#error No cpu_init_crit() defined for current CPU type 414#endif 415 416#ifdef CONFIG_ARM7_REVD 417 /* set clock speed */ 418 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ 419 /* !!! not doing DRAM refresh properly! */ 420 ldr r0, SYSCON3 421 ldr r1, [r0] 422 bic r1, r1, #CLKCTL 423 orr r1, r1, #CLKCTL_36 424 str r1, [r0] 425#endif 426 427#ifndef CONFIG_LPC2292 428 mov ip, lr 429 /* 430 * before relocating, we have to setup RAM timing 431 * because memory timing is board-dependent, you will 432 * find a lowlevel_init.S in your board directory. 433 */ 434 bl lowlevel_init 435 mov lr, ip 436#endif 437 438 mov pc, lr 439 440 441#ifndef CONFIG_SPL_BUILD 442/* 443 ************************************************************************* 444 * 445 * Interrupt handling 446 * 447 ************************************************************************* 448 */ 449 450@ 451@ IRQ stack frame. 452@ 453#define S_FRAME_SIZE 72 454 455#define S_OLD_R0 68 456#define S_PSR 64 457#define S_PC 60 458#define S_LR 56 459#define S_SP 52 460 461#define S_IP 48 462#define S_FP 44 463#define S_R10 40 464#define S_R9 36 465#define S_R8 32 466#define S_R7 28 467#define S_R6 24 468#define S_R5 20 469#define S_R4 16 470#define S_R3 12 471#define S_R2 8 472#define S_R1 4 473#define S_R0 0 474 475#define MODE_SVC 0x13 476#define I_BIT 0x80 477 478/* 479 * use bad_save_user_regs for abort/prefetch/undef/swi ... 480 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 481 */ 482 483 .macro bad_save_user_regs 484 sub sp, sp, #S_FRAME_SIZE 485 stmia sp, {r0 - r12} @ Calling r0-r12 486 add r8, sp, #S_PC 487 488 ldr r2, IRQ_STACK_START_IN 489 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 490 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 491 492 add r5, sp, #S_SP 493 mov r1, lr 494 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 495 mov r0, sp 496 .endm 497 498 .macro irq_save_user_regs 499 sub sp, sp, #S_FRAME_SIZE 500 stmia sp, {r0 - r12} @ Calling r0-r12 501 add r8, sp, #S_PC 502 stmdb r8, {sp, lr}^ @ Calling SP, LR 503 str lr, [r8, #0] @ Save calling PC 504 mrs r6, spsr 505 str r6, [r8, #4] @ Save CPSR 506 str r0, [r8, #8] @ Save OLD_R0 507 mov r0, sp 508 .endm 509 510 .macro irq_restore_user_regs 511 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 512 mov r0, r0 513 ldr lr, [sp, #S_PC] @ Get PC 514 add sp, sp, #S_FRAME_SIZE 515 subs pc, lr, #4 @ return & move spsr_svc into cpsr 516 .endm 517 518 .macro get_bad_stack 519 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 520 521 str lr, [r13] @ save caller lr / spsr 522 mrs lr, spsr 523 str lr, [r13, #4] 524 525 mov r13, #MODE_SVC @ prepare SVC-Mode 526 msr spsr_c, r13 527 mov lr, pc 528 movs pc, lr 529 .endm 530 531 .macro get_irq_stack @ setup IRQ stack 532 ldr sp, IRQ_STACK_START 533 .endm 534 535 .macro get_fiq_stack @ setup FIQ stack 536 ldr sp, FIQ_STACK_START 537 .endm 538 539/* 540 * exception handlers 541 */ 542 .align 5 543undefined_instruction: 544 get_bad_stack 545 bad_save_user_regs 546 bl do_undefined_instruction 547 548 .align 5 549software_interrupt: 550 get_bad_stack 551 bad_save_user_regs 552 bl do_software_interrupt 553 554 .align 5 555prefetch_abort: 556 get_bad_stack 557 bad_save_user_regs 558 bl do_prefetch_abort 559 560 .align 5 561data_abort: 562 get_bad_stack 563 bad_save_user_regs 564 bl do_data_abort 565 566 .align 5 567not_used: 568 get_bad_stack 569 bad_save_user_regs 570 bl do_not_used 571 572#ifdef CONFIG_USE_IRQ 573 574 .align 5 575irq: 576 get_irq_stack 577 irq_save_user_regs 578 bl do_irq 579 irq_restore_user_regs 580 581 .align 5 582fiq: 583 get_fiq_stack 584 /* someone ought to write a more effiction fiq_save_user_regs */ 585 irq_save_user_regs 586 bl do_fiq 587 irq_restore_user_regs 588 589#else 590 591 .align 5 592irq: 593 get_bad_stack 594 bad_save_user_regs 595 bl do_irq 596 597 .align 5 598fiq: 599 get_bad_stack 600 bad_save_user_regs 601 bl do_fiq 602 603#endif 604#endif /* CONFIG_SPL_BUILD */ 605 606#if defined(CONFIG_NETARM) 607 .align 5 608.globl reset_cpu 609reset_cpu: 610 ldr r1, =NETARM_MEM_MODULE_BASE 611 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] 612 ldr r1, =0xFFFFF000 613 and r0, r1, r0 614 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE) 615 add r0, r1, r0 616 ldr r4, =NETARM_GEN_MODULE_BASE 617 ldr r1, =NETARM_GEN_SW_SVC_RESETA 618 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 619 ldr r1, =NETARM_GEN_SW_SVC_RESETB 620 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 621 ldr r1, =NETARM_GEN_SW_SVC_RESETA 622 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 623 ldr r1, =NETARM_GEN_SW_SVC_RESETB 624 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 625 mov pc, r0 626#elif defined(CONFIG_S3C4510B) 627/* Nothing done here as reseting the CPU is board specific, depending 628 * on external peripherals such as watchdog timers, etc. */ 629#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 630 /* No specific reset actions for IntegratorAP/CM720T as yet */ 631#elif defined(CONFIG_LPC2292) 632 .align 5 633.globl reset_cpu 634reset_cpu: 635 mov pc, r0 636#else 637#error No reset_cpu() defined for current CPU type 638#endif 639