pxa: Add code to examine cpu model and revision

Add function which return CPU model and revision which can be used for
cpu detection.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>

tegra: clean up board include hell

The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used

tegra: clean up board include hell

The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used. Consolidate this in a common board header.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra: add funcmux entry for NAND attached to KBC

Secondary config for the Flash attachment.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by:

tegra: add funcmux entry for NAND attached to KBC

Secondary config for the Flash attachment.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: rework UART GPIO handling

Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This

tegra20: rework UART GPIO handling

Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This allows
to simply call this function in early board init whether or not
we are building with CONFIG_UART_SWITCH defined.

Also provide a weak symbol for this function, to avoid the
need to provide this function for boards that don't need any
fixup.

This patch supersedes the earlier posted
"tegra: convert gpio_config_uart to weak symbol".
Build tested with MAKEALL -s tegra20

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: add clock_set_pllout function

Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware ge

tegra20: add clock_set_pllout function

Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: complete periph_id enum

Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by:

tegra20: complete periph_id enum

Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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Tegra20: Move some include files to arch-tegra for sharing with Tegra30

The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20

Tegra20: Move some include files to arch-tegra for sharing with Tegra30

The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>

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Tegra20: Move some code files to common directories for upcoming Tegra30 patches.

Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7)

Tegra20: Move some code files to common directories for upcoming Tegra30 patches.

Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.

Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.

Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.

Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra20: add USB ULPI init code

This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along

tegra20: add USB ULPI init code

This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.

To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>

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tegra20: port to new ehci interface

EHCI interface now supports more than one controller. Wire up our usb functions
to use this new interface.

Signed-off-by: Lucas Stach <dev@lynxeye.de>

usb: lowlevel interface change to support multiple controllers

Carry an index in the lowlevel usb functions to make specify the
respective usb controller.

Also pass through an controller struct fro

usb: lowlevel interface change to support multiple controllers

Carry an index in the lowlevel usb functions to make specify the
respective usb controller.

Also pass through an controller struct from lowlevel_init to the
creation of the root usb device of this controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>

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serial: mxs: spl: Remove empty serial_* functions from SPL code

Remove the empty bodies from serial_* functions from MXS SPL code.
These empty implementations are now in common/serial.c instead so
d

serial: mxs: spl: Remove empty serial_* functions from SPL code

Remove the empty bodies from serial_* functions from MXS SPL code.
These empty implementations are now in common/serial.c instead so
declaring them also in the SPL code would cause a colision once
serial multi is enabled unconditionally.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefano Babic <sbabic@denx.de>

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ARM: prevent misaligned array inits

Under option -munaligned-access, gcc can perform local char
or 16-bit array initializations using misaligned native
accesses which will throw a data abort excepti

ARM: prevent misaligned array inits

Under option -munaligned-access, gcc can perform local char
or 16-bit array initializations using misaligned native
accesses which will throw a data abort exception. Fix files
where these array initializations were unneeded, and for
files known to contain such initializations, enforce gcc
option -mno-unaligned-access.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Switch to usign call cc-option for -mno-unaligned-access as
Albert had done previously as that's really correct]
Signed-off-by: Tom Rini <trini@ti.com>

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arm: armv7: omap3: Fix restore sequence in lowlevel_init

The restore sequence in lowlevel_init was in the wrong order,
causing lr to lose its original value and be set equal to ip
instead. Also, its

arm: armv7: omap3: Fix restore sequence in lowlevel_init

The restore sequence in lowlevel_init was in the wrong order,
causing lr to lose its original value and be set equal to ip
instead. Also, its use of the stack clashes with that of
s_init, so move the s_init call after the restore and turn
it into a tail-optimized branch.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>

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arm: rmobile: bugfix: wrong register saving in lowlevel_init

lowlevel_init() of rmobile badly assumed that ip register holds return address.
The commit "63ee53a7 armv7 cpu_init_crit: Simplify code"

arm: rmobile: bugfix: wrong register saving in lowlevel_init

lowlevel_init() of rmobile badly assumed that ip register holds return address.
The commit "63ee53a7 armv7 cpu_init_crit: Simplify code" breaks this assumption.
This patch removes this bad assumption and simplify code.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>

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arm: armv7: temporarily set -mno-unaligned-access

This patch aims at ensuring that the 2012.10 release works
out-of-the-box on as many targets as possible, by reinstating
commit 5347560f5427bcdd48a5

arm: armv7: temporarily set -mno-unaligned-access

This patch aims at ensuring that the 2012.10 release works
out-of-the-box on as many targets as possible, by reinstating
commit 5347560f5427bcdd48a563b62180481606ac8044, which adds
option -mno-unaligned-access to armv7 builds.

This patch will be overriden immediately after release of 2012.10.

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ARM: Add Altera SOCFPGA Cyclone5

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
Signe

ARM: Add Altera SOCFPGA Cyclone5

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Tom Trini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
----
v8: Remove no_return attribute for reset_cpu

Based on v2012.10-rc2

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arm: Support new Xilinx Zynq platform

Add timer driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Mare

arm: Support new Xilinx Zynq platform

Add timer driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

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arm: Fixed the offset for the no relocation.

When the u-boot address of destination equal to __start,
no relocation. relocation offset(r9) = 0.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Tes

arm: Fixed the offset for the no relocation.

When the u-boot address of destination equal to __start,
no relocation. relocation offset(r9) = 0.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Tested-by: Stefano Babic <sbabic@denx.de>

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arm: Remove additional config flags

These options are just duplicated from arch/arm/cpu/armv7/config.mk

Signed-off-by: Michal Simek <monstr@monstr.eu>

armv7 cpu_init_crit: Simplify code

We don't need to return to cpu_init_crit after calling lowlevel_init, so
lowlevel_init can directly return to the caller of cpu_init_crit.

Signed-off-by: Benoît T

armv7 cpu_init_crit: Simplify code

We don't need to return to cpu_init_crit after calling lowlevel_init, so
lowlevel_init can directly return to the caller of cpu_init_crit.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

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kirkwood: implement kw_sdram_size_adjust

Size of the SDRAM chips might differ between any two (otherwise
identical) instances of the same board.

So add a function kw_sdram_size_adjust() which reads

kirkwood: implement kw_sdram_size_adjust

Size of the SDRAM chips might differ between any two (otherwise
identical) instances of the same board.

So add a function kw_sdram_size_adjust() which reads out the current
ram size for a given bank, and adjusts the Kirkwood's SDRAM window size
register accordingly.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>

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kirkwood: implement kw_sdram_bs_set()

Some boards might be equipped with different SDRAM configurations.
When that is the case, CPU CS Window Size Register (CS[0]n Size)
should be set to the biggest

kirkwood: implement kw_sdram_bs_set()

Some boards might be equipped with different SDRAM configurations.
When that is the case, CPU CS Window Size Register (CS[0]n Size)
should be set to the biggest value through board.cfg file; then its
value can be fixed at runtime according to the detected SDRAM size.

Therefore, implement kw_sdram_bs_set().

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>

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kirkwood: use c-struct for access to SDRAM addr decode registers

Remove the defines and do this with a C-struct.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <praf

kirkwood: use c-struct for access to SDRAM addr decode registers

Remove the defines and do this with a C-struct.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>

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rmobile: Fix build timer driver with BUILD_DIR

Rmobile common timer driver diverts the same driver as SH architecture.
When it builds at the same place with source, it is no problem, but when
it bu

rmobile: Fix build timer driver with BUILD_DIR

Rmobile common timer driver diverts the same driver as SH architecture.
When it builds at the same place with source, it is no problem, but when
it builds out of source, it cannot build.
This patch revises this problem.

Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

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