1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 /* Tegra clock control functions */ 23 24 #ifndef _CLOCK_H 25 #define _CLOCK_H 26 27 /* Set of oscillator frequencies supported in the internal API. */ 28 enum clock_osc_freq { 29 /* All in MHz, so 13_0 is 13.0MHz */ 30 CLOCK_OSC_FREQ_13_0, 31 CLOCK_OSC_FREQ_19_2, 32 CLOCK_OSC_FREQ_12_0, 33 CLOCK_OSC_FREQ_26_0, 34 35 CLOCK_OSC_FREQ_COUNT, 36 }; 37 38 #include <asm/arch/clock-tables.h> 39 /* PLL stabilization delay in usec */ 40 #define CLOCK_PLL_STABLE_DELAY_US 300 41 42 /* return the current oscillator clock frequency */ 43 enum clock_osc_freq clock_get_osc_freq(void); 44 45 /** 46 * Start PLL using the provided configuration parameters. 47 * 48 * @param id clock id 49 * @param divm input divider 50 * @param divn feedback divider 51 * @param divp post divider 2^n 52 * @param cpcon charge pump setup control 53 * @param lfcon loop filter setup control 54 * 55 * @returns monotonic time in us that the PLL will be stable 56 */ 57 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 58 u32 divp, u32 cpcon, u32 lfcon); 59 60 /** 61 * Read low-level parameters of a PLL. 62 * 63 * @param id clock id to read (note: USB is not supported) 64 * @param divm returns input divider 65 * @param divn returns feedback divider 66 * @param divp returns post divider 2^n 67 * @param cpcon returns charge pump setup control 68 * @param lfcon returns loop filter setup control 69 * 70 * @returns 0 if ok, -1 on error (invalid clock id) 71 */ 72 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 73 u32 *divp, u32 *cpcon, u32 *lfcon); 74 75 /* 76 * Enable a clock 77 * 78 * @param id clock id 79 */ 80 void clock_enable(enum periph_id clkid); 81 82 /* 83 * Disable a clock 84 * 85 * @param id clock id 86 */ 87 void clock_disable(enum periph_id clkid); 88 89 /* 90 * Set whether a clock is enabled or disabled. 91 * 92 * @param id clock id 93 * @param enable 1 to enable, 0 to disable 94 */ 95 void clock_set_enable(enum periph_id clkid, int enable); 96 97 /** 98 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 99 * it out of reset and waits for th delay again. 100 * 101 * @param periph_id peripheral to reset 102 * @param us_delay time to delay in microseconds 103 */ 104 void reset_periph(enum periph_id periph_id, int us_delay); 105 106 /** 107 * Put a peripheral into or out of reset. 108 * 109 * @param periph_id peripheral to reset 110 * @param enable 1 to put into reset, 0 to take out of reset 111 */ 112 void reset_set_enable(enum periph_id periph_id, int enable); 113 114 115 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 116 enum crc_reset_id { 117 /* Things we can hold in reset for each CPU */ 118 crc_rst_cpu = 1, 119 crc_rst_de = 1 << 2, /* What is de? */ 120 crc_rst_watchdog = 1 << 3, 121 crc_rst_debug = 1 << 4, 122 }; 123 124 /** 125 * Put parts of the CPU complex into or out of reset.\ 126 * 127 * @param cpu cpu number (0 or 1 on Tegra2) 128 * @param which which parts of the complex to affect (OR of crc_reset_id) 129 * @param reset 1 to assert reset, 0 to de-assert 130 */ 131 void reset_cmplx_set_enable(int cpu, int which, int reset); 132 133 /** 134 * Set the source for a peripheral clock. This plus the divisor sets the 135 * clock rate. You need to look up the datasheet to see the meaning of the 136 * source parameter as it changes for each peripheral. 137 * 138 * Warning: This function is only for use pre-relocation. Please use 139 * clock_start_periph_pll() instead. 140 * 141 * @param periph_id peripheral to adjust 142 * @param source source clock (0, 1, 2 or 3) 143 */ 144 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 145 146 /** 147 * Set the source and divisor for a peripheral clock. This sets the 148 * clock rate. You need to look up the datasheet to see the meaning of the 149 * source parameter as it changes for each peripheral. 150 * 151 * Warning: This function is only for use pre-relocation. Please use 152 * clock_start_periph_pll() instead. 153 * 154 * @param periph_id peripheral to adjust 155 * @param source source clock (0, 1, 2 or 3) 156 * @param divisor divisor value to use 157 */ 158 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 159 unsigned divisor); 160 161 /** 162 * Start a peripheral PLL clock at the given rate. This also resets the 163 * peripheral. 164 * 165 * @param periph_id peripheral to start 166 * @param parent PLL id of required parent clock 167 * @param rate Required clock rate in Hz 168 * @return rate selected in Hz, or -1U if something went wrong 169 */ 170 unsigned clock_start_periph_pll(enum periph_id periph_id, 171 enum clock_id parent, unsigned rate); 172 173 /** 174 * Returns the rate of a peripheral clock in Hz. Since the caller almost 175 * certainly knows the parent clock (having just set it) we require that 176 * this be passed in so we don't need to work it out. 177 * 178 * @param periph_id peripheral to start 179 * @param parent PLL id of parent clock (used to calculate rate, you 180 * must know this!) 181 * @return clock rate of peripheral in Hz 182 */ 183 unsigned long clock_get_periph_rate(enum periph_id periph_id, 184 enum clock_id parent); 185 186 /** 187 * Adjust peripheral PLL clock to the given rate. This does not reset the 188 * peripheral. If a second stage divisor is not available, pass NULL for 189 * extra_div. If it is available, then this parameter will return the 190 * divisor selected (which will be a power of 2 from 1 to 256). 191 * 192 * @param periph_id peripheral to start 193 * @param parent PLL id of required parent clock 194 * @param rate Required clock rate in Hz 195 * @param extra_div value for the second-stage divisor (NULL if one is 196 not available) 197 * @return rate selected in Hz, or -1U if something went wrong 198 */ 199 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 200 enum clock_id parent, unsigned rate, int *extra_div); 201 202 /** 203 * Returns the clock rate of a specified clock, in Hz. 204 * 205 * @param parent PLL id of clock to check 206 * @return rate of clock in Hz 207 */ 208 unsigned clock_get_rate(enum clock_id clkid); 209 210 /** 211 * Start up a UART using low-level calls 212 * 213 * Prior to relocation clock_start_periph_pll() cannot be called. This 214 * function provides a way to set up a UART using low-level calls which 215 * do not require BSS. 216 * 217 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 218 */ 219 void clock_ll_start_uart(enum periph_id periph_id); 220 221 /** 222 * Decode a peripheral ID from a device tree node. 223 * 224 * This works by looking up the peripheral's 'clocks' node and reading out 225 * the second cell, which is the clock number / peripheral ID. 226 * 227 * @param blob FDT blob to use 228 * @param node Node to look at 229 * @return peripheral ID, or PERIPH_ID_NONE if none 230 */ 231 enum periph_id clock_decode_periph_id(const void *blob, int node); 232 233 /** 234 * Checks if the oscillator bypass is enabled (XOBP bit) 235 * 236 * @return 1 if bypass is enabled, 0 if not 237 */ 238 int clock_get_osc_bypass(void); 239 240 /* 241 * Checks that clocks are valid and prints a warning if not 242 * 243 * @return 0 if ok, -1 on error 244 */ 245 int clock_verify(void); 246 247 /* Initialize the clocks */ 248 void clock_init(void); 249 250 /* Initialize the PLLs */ 251 void clock_early_init(void); 252 253 #endif /* _CLOCK_H_ */ 254