| 8303ed12 | 21-Jan-2013 |
Marek Vasut <marex@denx.de> |
mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into the DRAM chip, thus caused occasional memory corruption. Fix this.
Signed-off-by: Marek Vasut <m
mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into the DRAM chip, thus caused occasional memory corruption. Fix this.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
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| 71a988aa | 18-Jan-2013 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
The mkimage command which uses this preprocessor output was
imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile
.gitignore was updated to ignore .cfgtmp files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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| 00239977 | 19-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these.
Signed-off-
mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these.
Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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| 30af6c0b | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mxs: Fix the memory init for MX23
The memory init is slightly different on MX23, thus split the memory init for mx23 and mx28 into different functions.
Signed-off-by: Marek Vasut <marex@denx.de> Si
mxs: Fix the memory init for MX23
The memory init is slightly different on MX23, thus split the memory init for mx23 and mx28 into different functions.
Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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| 7788bf06 | 11-Jan-2013 |
Marek Vasut <marex@denx.de> |
mxs: Add function to ungate the power block on MX23
The power block on MX23 must first be ungated before it can be operated. Add function to MXS power init that ungates it.
Signed-off-by: Marek Vas
mxs: Add function to ungate the power block on MX23
The power block on MX23 must first be ungated before it can be operated. Add function to MXS power init that ungates it.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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| e6d93c26 | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mx23: config: Enable building of u-boot.sb binary
For i.MX23 we need to pass imx23 as elftosb param.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freesc
mx23: config: Enable building of u-boot.sb binary
For i.MX23 we need to pass imx23 as elftosb param.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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| 1ddf386e | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mx23: SPL: Initialize DDR at 133MHz
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic
mx23: SPL: Initialize DDR at 133MHz
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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| f942f7d9 | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mx23: SPL: Add boot mode support
This adds the boot mode support for i.MX23 processors.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc:
mx23: SPL: Add boot mode support
This adds the boot mode support for i.MX23 processors.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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| f69077e4 | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mx23: Add support on print_cpuinfo()
Add information to identify i.MX23 chips and its known revisions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@free
mx23: Add support on print_cpuinfo()
Add information to identify i.MX23 chips and its known revisions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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| bf48fcb6 | 11-Jan-2013 |
Otavio Salvador <otavio@ossystems.com.br> |
mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <s
mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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| 14e26bcf | 11-Jan-2013 |
Marek Vasut <marex@denx.de> |
mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one
mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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| d08b9e9c | 09-Jan-2013 |
Allen Martin <amartin@nvidia.com> |
tegra: remove IRDA pinmux synonym
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate.
Signed-off-by: Allen Martin <amartin@nvidia.c
tegra: remove IRDA pinmux synonym
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate.
Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 619bd99e | 21-Dec-2012 |
Tom Warren <twarren@nvidia.com> |
Tegra30: clocks: Fix clock tables for I2C and other periphs
Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function.
Signed-off-by: Tom W
Tegra30: clocks: Fix clock tables for I2C and other periphs
Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function.
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 6d6c0bae | 11-Dec-2012 |
Tom Warren <twarren.nvidia@gmail.com> |
Tegra30: Add generic Tegra30 build support
This patch adds basic Tegra30 (T30) build support - no specific board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen War
Tegra30: Add generic Tegra30 build support
This patch adds basic Tegra30 (T30) build support - no specific board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
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| b2871037 | 11-Dec-2012 |
Tom Warren <twarren.nvidia@gmail.com> |
Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences.
Signed-off-by: Tom Warren <twarren@
Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
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| 5576aab5 | 11-Dec-2012 |
Tom Warren <twarren.nvidia@gmail.com> |
Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards. At this time, there are no T30-specific ARMV7 files. As T30-specific run-time code is added, it'll go
Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards. At this time, there are no T30-specific ARMV7 files. As T30-specific run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidai.com>
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| 1b245fee | 11-Dec-2012 |
Tom Warren <twarren.nvidia@gmail.com> |
Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines i
Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines into tegra-common/cpu.c and reduce code duplication.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
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| df3ad6c8 | 12-Jan-2013 |
Łukasz Dałek <luk0104@gmail.com> |
pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling cpu_init_crit by BL instruction. BL is overwriting lr register so relocate_code i
pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling cpu_init_crit by BL instruction. BL is overwriting lr register so relocate_code is going into infinite loop. This patch preservs lr register in r12 before calling cpu_init_crit and after function returns restores it.
Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
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| a17617d6 | 14-Jan-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' |
| 1199c377 | 14-Jan-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' |
| abbab703 | 22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> |
| 5374d386 | 27-Dec-2012 |
Jaehoon Chung <jh80.chung@samsung.com> |
Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk
Mobile storage is used the CLK_DIV_FSYS3 value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@sam
Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk
Mobile storage is used the CLK_DIV_FSYS3 value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| c39e969e | 27-Dec-2012 |
Jaehoon Chung <jh80.chung@samsung.com> |
Exynos: clock: support get_mmc_clk for exynos
To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk().
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
Exynos: clock: support get_mmc_clk for exynos
To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk().
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 1673f199 | 08-Jan-2013 |
Ajay Kumar <ajaykumar.rs@samsung.com> |
EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue.
EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 612404c2 | 09-Jan-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge 'u-boot-atmel/master' into 'u-boot-arm/master' |