sun6i: Poke magic sram controller register to avoid cache issues

Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by

sun6i: Poke magic sram controller register to avoid cache issues

Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sun6i: Add dram initialization code

Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based

sun6i: Add dram initialization code

Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sun4i: Rename dram files to dram_sun4i.x

In preparation for adding sun6i dram support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

sun6i: Add cpucfg register definitions

Not used atm, for future use (e.g. PSCI).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

sun6i: Add clock functions needed for SPL / DRAM init

Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add so

sun6i: Add clock functions needed for SPL / DRAM init

Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sun6i: Add new p2wi controller driver

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, t

sun6i: Add new p2wi controller driver

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

kconfig: arm: move "armv8" define to arch/arm/Kconfig

Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs)
collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig.

This co

kconfig: arm: move "armv8" define to arch/arm/Kconfig

Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs)
collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig.

This commit moves "armv8" to there for consistency.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>

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kconfig: arm: select CPU_V7 for some new boards

This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

Redu

kconfig: arm: select CPU_V7 for some new boards

This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

Redundant "SYS_CPU" defines and "string" directives should be removed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>

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ARM: remove unused CPU directory

There is no board with CPU "arm_intcm".

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

arm: imx: make bmode command work with SPL/U-Boot combo

The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change usi

arm: imx: make bmode command work with SPL/U-Boot combo

The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.

SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.

The result is that the selected boot device is not used across all
the boot stages.

Update spl_boot_device() to look at gpr9 when necessary.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Heiko Schocher <hs@denx.de>

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ARM: cache_v7: Various minor cleanups

Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable dec

ARM: cache_v7: Various minor cleanups

Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable declaration section to a separate line (rather than the
one with the opening brace) and keeps the function signature on a single
line where possible.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

ARM: UniPhier: call pin_init() also in the normal boot

CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the

ARM: UniPhier: call pin_init() also in the normal boot

CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the normal image
so that UART works correctly.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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ARM: UniPhier: consolidate board_postclk_init() function

This commit merges
arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
arch/arm/cpu/armv7/uniphier/board_postclk_init.c

Because PH

ARM: UniPhier: consolidate board_postclk_init() function

This commit merges
arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
arch/arm/cpu/armv7/uniphier/board_postclk_init.c

Because PH1-Pro4 does not have the BCU block, add __weak to
bcu_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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usb: UniPhier: add UniPhier on-chip EHCI host driver support

Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB

usb: UniPhier: add UniPhier on-chip EHCI host driver support

Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).

TODO for me:
Move the base address to device trees.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>

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ARM: UniPhier: add EHCI host pin settings for PH1-Pro4

These IO pins are necessary for port power control and
over current detect.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

ARM: UniPhier: move DDR related configuration to Kconfig

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

ARM: UniPhier: reset on-board devices on start-up

If a support card is attached to the main board, the on-board
SMSC9118 LAN controller is available. It must be kept in reset
state for a while on s

ARM: UniPhier: reset on-board devices on start-up

If a support card is attached to the main board, the on-board
SMSC9118 LAN controller is available. It must be kept in reset
state for a while on start-up.

When the board is kicked via a debbuger rather than pushing the
hardware reset button, on-board chips are not reset; in this case
the reset signals should be asserted by software.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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kconfig: zynq: Add ZYBO board

Add a defconfig and Kconfigury for the Digilent ZYBO board.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaga

kconfig: zynq: Add ZYBO board

Add a defconfig and Kconfigury for the Digilent ZYBO board.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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ARM: MXS: fix Uninitialized variable error

cppcheck reports:

[arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized
variable: now

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut

ARM: MXS: fix Uninitialized variable error

cppcheck reports:

[arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized
variable: now

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

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arm: rmobile: Add support gose board

The gose board has R8A7793, 1GB DDR3-SDRAM, USB, Ethernet, and more.
This patch supports the following functions:
- DDR3-SDRAM
- SCIF
- QSPI
- SPI

Signed-of

arm: rmobile: Add support gose board

The gose board has R8A7793, 1GB DDR3-SDRAM, USB, Ethernet, and more.
This patch supports the following functions:
- DDR3-SDRAM
- SCIF
- QSPI
- SPI

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

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arm: rmobile: Add support R8A7793

Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamur

arm: rmobile: Add support R8A7793

Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

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cppcheck cleanup: fix nullPointer errors

There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on system

cppcheck cleanup: fix nullPointer errors

There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on systems where these are located in low memory.

Add "cppcheck-suppress nullPointer" comments to silence cppcheck
where this is intentional and legal.

Signed-off-by: Wolfgang Denk <wd@denx.de>

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Merge git://git.denx.de/u-boot-ti