armv8: ls2080ardb: Add QSPI-boot support

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is no

armv8: ls2080ardb: Add QSPI-boot support

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Convert CONFIG_CMD_FUSE to Kconfig

This converts the following to Kconfig:
CONFIG_CMD_FUSE

Signed-off-by: Simon Glass <sjg@chromium.org>

icorem6: Make SPL to pick suitable fdt

SPL FIT is able to pick the suitable fdt file for u-boot,
so add that function through board_fit_config_name_match.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Mat

icorem6: Make SPL to pick suitable fdt

SPL FIT is able to pick the suitable fdt file for u-boot,
so add that function through board_fit_config_name_match.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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geam6ul: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMA

geam6ul: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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icorem6: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMA

icorem6: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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arch/arm/cpu/arm926ejs/omap: Remove

This code has been unused since the removal of the "omap2" platforms,
remove.

Signed-off-by: Tom Rini <trini@konsulko.com>

armv8: minor fix to comment for enabling SMPEN bit

The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling err

armv8: minor fix to comment for enabling SMPEN bit

The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling error.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
CC: York Sun <york.sun@nxp.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv7m: add MPU configuration support

Cortex-M archs support option memory protection unit (MPU). MPU is used
to set the memory types, attributes, access permissions for different regions,
cache pol

armv7m: add MPU configuration support

Cortex-M archs support option memory protection unit (MPU). MPU is used
to set the memory types, attributes, access permissions for different regions,
cache policies of the device.

e.g. using MPU it is possible to configure memory region as device memory
or strongly ordered, memory attributes like execute never, cache policies
like write-back or write-through.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

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arvm7m: add cleanup before linux booting

Data cache memory needs to be disabled before handing over control to
linux kernel. This patch populates the cleanup_before_linux stub.

Signed-off-by: Vikas

arvm7m: add cleanup before linux booting

Data cache memory needs to be disabled before handing over control to
linux kernel. This patch populates the cleanup_before_linux stub.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

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armv7m: cache: add flush & invalidate all dcache

Add functionality to flush & invalidate all the dcache using the
prototype declared in common header file.

Signed-off-by: Vikas Manocha <vikas.manoc

armv7m: cache: add flush & invalidate all dcache

Add functionality to flush & invalidate all the dcache using the
prototype declared in common header file.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add dummy functions for the not-enabled case]
Signed-off-by: Tom Rini <trini@konsulko.com>

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arm: Support cache invalidate

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operat

arm: Support cache invalidate

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

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arm: Correct signature for get_ticks()

This should be uint64_t to match its definition in common.h. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add ARM errata workaround 852421 and 852423 for Cortex-A17

ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and

Add ARM errata workaround 852421 and 852423 for Cortex-A17

ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.

Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>

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fdt: Move fdt_fixup_ethernet to a common place

With 3f66149d9fb4 we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup.

fdt: Move fdt_fixup_ethernet to a common place

With 3f66149d9fb4 we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup. On ARM however we largely relied on this call. Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location. Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d9fb4 ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Re-sync ARCH_MX5 / MX51 / MX53 CONFIG options

A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 /
CONFIG_MX53 being in Kconfig. Do so now.

Signed-off-by: Tom Rini <

arm: Re-sync ARCH_MX5 / MX51 / MX53 CONFIG options

A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 /
CONFIG_MX53 being in Kconfig. Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-sunxi

arm: psci: make psci usable on single core socs

PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this

arm: psci: make psci usable on single core socs

PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.

Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Add validation of PPA image from NAND and SD

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinit

armv8: fsl-layerscape: Add validation of PPA image from NAND and SD

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash

Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.

Signed-off-by: Sumit Garg <sumit.garg@nxp

armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash

Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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sunxi: Add PSCI support for R40

The R40's CPU controls are a combination of sun6i and sun7i.

All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, p

sunxi: Add PSCI support for R40

The R40's CPU controls are a combination of sun6i and sun7i.

All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.

Last, the R40 does not have a secure SRAM block.

This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

ARM: adjust arm-smccc code for use in U-Boot

Adjust ARM SMC Calling Convention code for U-Boot:
- Replace the license block with SPDX
- Change path to asm-offsets.h
- Define UNWIND() as no-op

ARM: adjust arm-smccc code for use in U-Boot

Adjust ARM SMC Calling Convention code for U-Boot:
- Replace the license block with SPDX
- Change path to asm-offsets.h
- Define UNWIND() as no-op
- Add Kconfig entry
- Add asm-offsets

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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ARM: import arm-smccc code from Linux 4.11-rc6

Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:

[Linux] [U-Boot]
arch/ar

ARM: import arm-smccc code from Linux 4.11-rc6

Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:

[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ

Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any

armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ

Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups

Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.

Signed-off-by: Prabhaka

armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups

Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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