1 /* 2 * Copyright (C) 2017 NXP Semiconductors 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <malloc.h> 9 #include <errno.h> 10 #include <netdev.h> 11 #include <fsl_ifc.h> 12 #include <fsl_ddr.h> 13 #include <asm/io.h> 14 #include <hwconfig.h> 15 #include <fdt_support.h> 16 #include <libfdt.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <efi_loader.h> 20 #include <i2c.h> 21 #include <asm/arch/mmu.h> 22 #include <asm/arch/soc.h> 23 #include <asm/arch/ppa.h> 24 #include <fsl_sec.h> 25 26 #ifdef CONFIG_FSL_QIXIS 27 #include "../common/qixis.h" 28 #include "ls2080ardb_qixis.h" 29 #endif 30 #include "../common/vid.h" 31 32 #define PIN_MUX_SEL_SDHC 0x00 33 #define PIN_MUX_SEL_DSPI 0x0a 34 35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 36 DECLARE_GLOBAL_DATA_PTR; 37 38 enum { 39 MUX_TYPE_SDHC, 40 MUX_TYPE_DSPI, 41 }; 42 43 unsigned long long get_qixis_addr(void) 44 { 45 unsigned long long addr; 46 47 if (gd->flags & GD_FLG_RELOC) 48 addr = QIXIS_BASE_PHYS; 49 else 50 addr = QIXIS_BASE_PHYS_EARLY; 51 52 /* 53 * IFC address under 256MB is mapped to 0x30000000, any address above 54 * is mapped to 0x5_10000000 up to 4GB. 55 */ 56 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 57 58 return addr; 59 } 60 61 int checkboard(void) 62 { 63 #ifdef CONFIG_FSL_QIXIS 64 u8 sw; 65 #endif 66 char buf[15]; 67 68 cpu_name(buf); 69 printf("Board: %s-RDB, ", buf); 70 71 #ifdef CONFIG_FSL_QIXIS 72 sw = QIXIS_READ(arch); 73 printf("Board Arch: V%d, ", sw >> 4); 74 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 75 76 sw = QIXIS_READ(brdcfg[0]); 77 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 78 79 if (sw < 0x8) 80 printf("vBank: %d\n", sw); 81 else if (sw == 0x9) 82 puts("NAND\n"); 83 else 84 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 85 86 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 87 #endif 88 puts("SERDES1 Reference : "); 89 printf("Clock1 = 156.25MHz "); 90 printf("Clock2 = 156.25MHz"); 91 92 puts("\nSERDES2 Reference : "); 93 printf("Clock1 = 100MHz "); 94 printf("Clock2 = 100MHz\n"); 95 96 return 0; 97 } 98 99 unsigned long get_board_sys_clk(void) 100 { 101 #ifdef CONFIG_FSL_QIXIS 102 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 103 104 switch (sysclk_conf & 0x0F) { 105 case QIXIS_SYSCLK_83: 106 return 83333333; 107 case QIXIS_SYSCLK_100: 108 return 100000000; 109 case QIXIS_SYSCLK_125: 110 return 125000000; 111 case QIXIS_SYSCLK_133: 112 return 133333333; 113 case QIXIS_SYSCLK_150: 114 return 150000000; 115 case QIXIS_SYSCLK_160: 116 return 160000000; 117 case QIXIS_SYSCLK_166: 118 return 166666666; 119 } 120 #endif 121 return 100000000; 122 } 123 124 int select_i2c_ch_pca9547(u8 ch) 125 { 126 int ret; 127 128 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 129 if (ret) { 130 puts("PCA: failed to select proper channel\n"); 131 return ret; 132 } 133 134 return 0; 135 } 136 137 int i2c_multiplexer_select_vid_channel(u8 channel) 138 { 139 return select_i2c_ch_pca9547(channel); 140 } 141 142 int config_board_mux(int ctrl_type) 143 { 144 #ifdef CONFIG_FSL_QIXIS 145 u8 reg5; 146 147 reg5 = QIXIS_READ(brdcfg[5]); 148 149 switch (ctrl_type) { 150 case MUX_TYPE_SDHC: 151 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 152 break; 153 case MUX_TYPE_DSPI: 154 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 155 break; 156 default: 157 printf("Wrong mux interface type\n"); 158 return -1; 159 } 160 161 QIXIS_WRITE(brdcfg[5], reg5); 162 #endif 163 return 0; 164 } 165 166 int board_init(void) 167 { 168 char *env_hwconfig; 169 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 170 #ifdef CONFIG_FSL_MC_ENET 171 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 172 #endif 173 u32 val; 174 175 init_final_memctl_regs(); 176 177 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 178 179 env_hwconfig = getenv("hwconfig"); 180 181 if (hwconfig_f("dspi", env_hwconfig) && 182 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 183 config_board_mux(MUX_TYPE_DSPI); 184 else 185 config_board_mux(MUX_TYPE_SDHC); 186 187 #ifdef CONFIG_ENV_IS_NOWHERE 188 gd->env_addr = (ulong)&default_environment[0]; 189 #endif 190 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 191 192 #ifdef CONFIG_FSL_QIXIS 193 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 194 #endif 195 #ifdef CONFIG_FSL_LS_PPA 196 ppa_init(); 197 #endif 198 199 #ifdef CONFIG_FSL_MC_ENET 200 /* invert AQR405 IRQ pins polarity */ 201 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 202 #endif 203 #ifdef CONFIG_FSL_CAAM 204 sec_init(); 205 #endif 206 207 return 0; 208 } 209 210 int board_early_init_f(void) 211 { 212 fsl_lsch3_early_init_f(); 213 return 0; 214 } 215 216 int misc_init_r(void) 217 { 218 #ifdef CONFIG_FSL_QIXIS 219 u8 sw; 220 221 sw = QIXIS_READ(arch); 222 /* 223 * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator 224 * which needs to be programmed to enable high speed SD interface 225 * by setting GPIO4_10 output to zero 226 */ 227 if ((sw & 0xf) == 0x5) { 228 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | 229 in_le32(GPIO4_GPDIR_ADDR))); 230 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & 231 in_le32(GPIO4_GPDAT_ADDR))); 232 } 233 #endif 234 235 if (hwconfig("sdhc")) 236 config_board_mux(MUX_TYPE_SDHC); 237 238 if (adjust_vdd(0)) 239 printf("Warning: Adjusting core voltage failed.\n"); 240 241 return 0; 242 } 243 244 void detail_board_ddr_info(void) 245 { 246 puts("\nDDR "); 247 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 248 print_ddr_info(0); 249 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 250 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 251 puts("\nDP-DDR "); 252 print_size(gd->bd->bi_dram[2].size, ""); 253 print_ddr_info(CONFIG_DP_DDR_CTRL); 254 } 255 #endif 256 } 257 258 #if defined(CONFIG_ARCH_MISC_INIT) 259 int arch_misc_init(void) 260 { 261 return 0; 262 } 263 #endif 264 265 #ifdef CONFIG_FSL_MC_ENET 266 void fdt_fixup_board_enet(void *fdt) 267 { 268 int offset; 269 270 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 271 272 if (offset < 0) 273 offset = fdt_path_offset(fdt, "/fsl-mc"); 274 275 if (offset < 0) { 276 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 277 __func__, offset); 278 return; 279 } 280 281 if (get_mc_boot_status() == 0) 282 fdt_status_okay(fdt, offset); 283 else 284 fdt_status_fail(fdt, offset); 285 } 286 287 void board_quiesce_devices(void) 288 { 289 fsl_mc_ldpaa_exit(gd->bd); 290 } 291 #endif 292 293 #ifdef CONFIG_OF_BOARD_SETUP 294 int ft_board_setup(void *blob, bd_t *bd) 295 { 296 u64 base[CONFIG_NR_DRAM_BANKS]; 297 u64 size[CONFIG_NR_DRAM_BANKS]; 298 299 ft_cpu_setup(blob, bd); 300 301 /* fixup DT for the two GPP DDR banks */ 302 base[0] = gd->bd->bi_dram[0].start; 303 size[0] = gd->bd->bi_dram[0].size; 304 base[1] = gd->bd->bi_dram[1].start; 305 size[1] = gd->bd->bi_dram[1].size; 306 307 #ifdef CONFIG_RESV_RAM 308 /* reduce size if reserved memory is within this bank */ 309 if (gd->arch.resv_ram >= base[0] && 310 gd->arch.resv_ram < base[0] + size[0]) 311 size[0] = gd->arch.resv_ram - base[0]; 312 else if (gd->arch.resv_ram >= base[1] && 313 gd->arch.resv_ram < base[1] + size[1]) 314 size[1] = gd->arch.resv_ram - base[1]; 315 #endif 316 317 fdt_fixup_memory_banks(blob, base, size, 2); 318 319 fsl_fdt_fixup_dr_usb(blob, bd); 320 321 #ifdef CONFIG_FSL_MC_ENET 322 fdt_fixup_board_enet(blob); 323 #endif 324 325 return 0; 326 } 327 #endif 328 329 void qixis_dump_switch(void) 330 { 331 #ifdef CONFIG_FSL_QIXIS 332 int i, nr_of_cfgsw; 333 334 QIXIS_WRITE(cms[0], 0x00); 335 nr_of_cfgsw = QIXIS_READ(cms[1]); 336 337 puts("DIP switch settings dump:\n"); 338 for (i = 1; i <= nr_of_cfgsw; i++) { 339 QIXIS_WRITE(cms[0], i); 340 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 341 } 342 #endif 343 } 344 345 /* 346 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 347 * Both slots has 0x54, resulting 2nd slot unusable. 348 */ 349 void update_spd_address(unsigned int ctrl_num, 350 unsigned int slot, 351 unsigned int *addr) 352 { 353 #ifdef CONFIG_FSL_QIXIS 354 u8 sw; 355 356 sw = QIXIS_READ(arch); 357 if ((sw & 0xf) < 0x3) { 358 if (ctrl_num == 1 && slot == 0) 359 *addr = SPD_EEPROM_ADDRESS4; 360 else if (ctrl_num == 1 && slot == 1) 361 *addr = SPD_EEPROM_ADDRESS3; 362 } 363 #endif 364 } 365