plat/marvell/armada: cleanup MSS SRAM if used for copy

This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).

Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
S

plat/marvell/armada: cleanup MSS SRAM if used for copy

This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).

Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

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plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage

Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows

plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage

Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>

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plat/marvell/armada/common/mss: use MSS SRAM in secure mode

The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image fro

plat/marvell/armada/common/mss: use MSS SRAM in secure mode

The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.

Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>

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driver: brcm: add mdio driver

Change-Id: Id873670f68a4c584e3b7b586cab28565bb5a1c27
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>

Merge "libc: memset: Fix MISRA issues" into integration

libc: memset: Fix MISRA issues

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also u

libc: memset: Fix MISRA issues

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.

Fix those issues to make the CI happy.

Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "plat:xilinx:zynqmp: Remove the custom crash implementation" into integration

plat:xilinx:zynqmp: Remove the custom crash implementation

Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.

Signed-off-by: Venkatesh Yadav Abbarapu <ven

plat:xilinx:zynqmp: Remove the custom crash implementation

Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215

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Merge "allwinner: Allow conditional compilation of SCPI and native PSCI ops" into integration

Merge "lib: cpus: aarch32: sanity check pointers before use" into integration

Merge "nand: stm32_fmc_nand: remove dead code" into integration

lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.ga

lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa

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Merge changes Ie5c48303,I5d363c46 into integration

* changes:
tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
tzc400: fix logical error in FILTER_BIT definitions

Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allw

Merge changes from topic "sunxi-split-psci" into integration

* changes:
allwinner: Split native and SCPI-based PSCI implementations
allwinner: psci: Improve system shutdown/reset sequence
allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
allwinner: Separate code to power off self and other CPUs

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Merge changes I8ea4ea58,I1f0b4aab,I2cccad40 into integration

* changes:
marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
marvell: uart: a3720: Update delay code to be compati

Merge changes I8ea4ea58,I1f0b4aab,I2cccad40 into integration

* changes:
marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
marvell: uart: a3720: Fix comments in console_a3700_core_init() function

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Merge "qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument" into integration

Merge "docs: stm32mp1: correct formatting issues" into integration

Merge "Revert "spmd: ensure SIMD context is saved/restored on SPMC entry/exit"" into integration

Merge "plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array" into integration

Revert "spmd: ensure SIMD context is saved/restored on SPMC entry/exit"

This reverts commit bedb13f509ac68adaf9baa9b5f24eede912e801d.
SIMD context is now saved in S-EL2 as opposed to EL3, see commit

Revert "spmd: ensure SIMD context is saved/restored on SPMC entry/exit"

This reverts commit bedb13f509ac68adaf9baa9b5f24eede912e801d.
SIMD context is now saved in S-EL2 as opposed to EL3, see commit:
https://review.trustedfirmware.org/c/hafnium/hafnium/+/8321

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic81416464ffada1a6348d0abdcf3adc7c1879e61

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plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array

Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platfo

plat/arm/css: rename rd_n1e1_edge_scmi_plat_info array

Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platforms and is not resitricted to only RD-N1 and RD-E1 platforms.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I42ba33e0afa3003c731ce513c6a5754b602ec01f

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plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface

Now that we have a framework for the SMCCC TRNG interface, and the
existing Juno entropy code has been prepared, add the few remainin

plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface

Now that we have a framework for the SMCCC TRNG interface, and the
existing Juno entropy code has been prepared, add the few remaining bits
to implement this interface for the Juno Trusted Entropy Source.

We retire the existing Juno specific RNG interface, and use the generic
one for the stack canary generation.

Change-Id: Ib6a6e5568cb8e0059d71740e2d18d6817b07127d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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docs: stm32mp1: correct formatting issues

Add blank lines before lists and code example.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6

marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms

TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so w

marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms

TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so wait at least 3ms
before flushing TX FIFO.

If WTMI firmware transmitted something via UART before TF-A was booted,
some characters may still wait in TX FIFO when TF-A is initializing UART
driver. So wait at least 3ms to ensure that HW has enough time to transmit
all characters waiting in TX FIFO.

This fixes an issue where sometimes characters transmitted on UART by our
custom WTMI image are lost.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19

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marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU

Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so i

marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU

Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
CPU is 600 MHz and in this case delay loop would take just 2 times more,
which is not a problem.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2

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